How AI is optimizing the IC test process Transcript – Part 1

In a recent podcast, Ron Press, Senior Director of Technology Enablement at Siemens Digital Industries discussed the ways AI is enhancing the Design For Test (DFT) process, and why both are such key elements of the semiconductor design and manufacturing process. Check out the episode here or keep reading for the transcript.

Spencer Acain: Hello, and welcome to the AI Spectrum podcast. I’m your host, Spencer Acain. In this series, we explore a wide range of AI topics from all across Siemens and how they’re applied to different technologies. Today, I’m joined by Ron Press, senior director of technology enablement at Siemens Digital Industries. Welcome, Ron.

Ron Press: Thank you, Spencer. Nice to be here.

Spencer Acain: So before we jump into this, can you give me just a little bit about your background and your work at Siemens?

Ron Press: Yeah. So I started in electronics test at Raytheon Company, and even back then, I did some research in ’93 on training neural networks to detect the built-in self-test false alarms. After Raytheon, I went to Harris RF and then joined Mentor Graphics, which later became Siemens, and mostly worked within the DFT area.

Spencer Acain: I see. So it sounds like you’ve got quite the history with test and artificial intelligence, so it’d be great if you could maybe give us a little background on what test is, what Tessent is, and how that works, just for our audience who might not know.

Ron Press: Sure. So Tessent, it started with just pure DFT, which is designed for test. It’s essentially looking at the semiconductor design and adjusting the circuit to make it easier to test, and then automatically creating test patterns for it. And this is whether it’s logic design or memory design, we do a memory build to self-test, and we also have diagnosis so when the tester runs these test patterns in production, if it fails, we can figure out what the root cause is. Some of the things we’ll talk about later is how we can use the scan diagnosis combined with all the fails we get in production to do a machine learning for big data analysis. And Tessent has expanded since then, and now we include embedded analytics, so we have monitors for in-life operation with our embedded analytics products.

Spencer Acain: All right. And so you mentioned test there, so can you maybe explain a little bit more what test is and why that’s important? What the value of this is? Why should we be designing these chips with test in mind? Like you said, that design for test tool or philosophy almost, what are some of the challenges with actually implementing that?

Ron Press: Yeah. So when semiconductor technology first started, the designs were fairly simple and people knew what the function was supposed to be. So after you fabricate the device, on the tester, you would say, “These inputs should result in this output,” and you would test it that way. But as semiconductor complexity and scaling advanced, it became too complicated for someone to know what’s the functional operation, and it would take too many states toggling the input values and clocking through sequential logic to get an output response. It was just overwhelming at some point in time.

So we developed, the industry when I say we, the industry developed a scan technology which converts all the sequential elements into big shift registers during test mode, so this way, we do a divide-and-conquer. We take the big complexity of the overall semiconductor design and break it into small combinational logic in between the sequential cells which are controllable and observable. And that allows us to do a very simple way to automatically create test patterns, and so that’s what is behind a lot of the DFT technology. We’re looking to make the design easier to test, remove any roadblocks, and as designs got more complicated, we added some sophistication on top of it to add automatic built in self test as well as embedded compression that allows us to test much more logic in a shorter time.

Spencer Acain: I see. And why would this be a key factor for designing these chips, being able to test them like this?

Ron Press: Right, because in the semiconductor manufacturing, if you tried to test with functional patterns, the quality of the test would be generally pretty low so you wouldn’t know if there are defects in the designs. You need an automatic way to be able to tell if there’s defects. And then in production, if you package a device and then put it in the final configuration, if it’s faulty, it’s very costly. So what we need to do is have a really high quality test that we can run during the semiconductor fabrication, so the wafer will run these patterns, and again, when they package the devices, they’ll often run the same patterns in the packaged part. But this is necessary just to ensure that the part is really functional before you either sell it to an end customer or you put it into a board or some other configuration.

Spencer Acain: Right. Yeah, it sounds like it would be extremely expensive if you’re shipping all these bad chips around, so you definitely need to make sure you’re able to catch all that ahead of time it sounds like.

Ron Press: Yes. And I guess I’ll add is the automotive industry, any defect that gets into the system is extremely expensive for them and it can cause a fatality. So even in the automotive industry, their defects per million devices that can escape production test, they want those defects per million to be in the single digits or less.

Spencer Acain: That must be incredibly difficult to achieve, that level of precision. You mentioned layering some kind of more advanced logic on top of this, and would that be AI and machine learning that you’re talking about here? And if so, how is Tessent leveraging these AI/ML technologies in the test process and what are some of the benefits you’re seeing out of that?

Ron Press: Yeah, so I guess there’s two areas I’ll mention with AI and what Tessent has been leveraging with AI. So one is as design scaling continued, we started to do designs hierarchically, so you would do a core design, you would put the DFT logic in that core design, you’d put your embedded compression, and then you’d create your patterns. And then when you finish all the different cores that are going into the final semiconductor design, you combine them together and then you’d have to figure out, well, what bandwidth from the IO pins am I sending to each of these cores so I can load my scan data? And there’s a bunch of trade-offs people would do to figure out how much bandwidth from the IO pin they’re going to send to each of these cores, and this was called hierarchical DFT.

But then what we’ve done is we realized, even if we applied AI to this problem, if we look at the end design with multiple cores in it and we optimize with AI to say what’s the best configuration for compression with each core and how much bandwidth from the IO pin should go to each core, our best result might be 20 to 30% smaller pattern size. What we decided to do was approach it differently. We looked at a completely different methodology in how we deliver the scan data. Instead of just wiring the IO pins of the semiconductor device to individual cores, what we did is we added something called streaming scan network. This is a packetized data delivery system, so we can take any number of pins at the chip level and feed with those pins this packetized bus, and that enables us to have any number of bits getting to a core that that core needs. So we can have a one bit bus and we can still deliver 16 bits for one core, four bits for another core, and so forth.

This way, instead of a user having to make trade-offs of how many of the IO they send to each core, we remove all those variables. They just optimize the core, make their patterns, and then in our software, in the SSN software, Streaming Scan Network software, we’re able to let that do the automatic optimization, so we call this analytical AI. So it optimizes to create a packetized data delivery system that balances the data that’s going to each cores, so the core tests will basically all finish around the same time.

Spencer Acain: So beyond the benefit you’ve already mentioned of having all of these tests ending at the same time, what makes Tessent take so well to machine learning? Is this something that you’ve worked toward over the years or is it just something that’s sprung naturally out of it?

Ron Press: Yeah, so scan data is kind of interesting. It has a massive amount of raw data available, so in one day,§ you might have thousands or tens of thousands of failing ICs. And for each failing IC, it’ll typically have a hundred or a few hundred failing patterns and thousands of passing patterns, and within each pattern, you can have millions or hundreds of millions of scan cell data points were it captured fail and passing data, so this is a massive amount of data. So if you work out the math, in any day, that’s essentially two times 10 to the 16 amount of raw data to work from.

So with scan diagnosis, we can take all this fail information, we can reverse it in the design and figure out what can explain the failing data on the production tester, and then as a digital twin of real failure analysis, we work out in software quickly, this is what we think the root cause is. And since we have so many failing devices available to us quickly, we can do this with every single failed device. That gives us a lot of data to use for machine learning.

And so our test into our root cause deconvolution, which is part of our yield learning product, this uses machine learning where we’ll train on whatever data’s relevant. So maybe if you have an excursion lot or excursion wafer, we’ll just train on that particular set of failing devices and we’ll find out, is there some type of systematic problem? The tool will find this for us and tell us, here’s something that you need to pay attention to and look at improving your yield of your production line.

And the types of results we have from this have been pretty significant. Some of our partners have published that even in mature production, one company reported that they were at 95% yield, and using our yield insight and root cause deconvolution machine learning, they found a systematic problem with Avia and they were able to improve the yield from 95 to 96.5%. That’s a pretty significant reduction in defective devices, so that can make millions of dollars a month impact in the profitability of a company.

Spencer Acain: That’s great. It sounds like you’ve really got a… That’s a pretty impressive tool you have there to make that kind of changes and to handle that kind of such large data structures and everything like that. But that is about all the time we have for this episode. So once again, I have been your host, Spencer Acain, joined by Ron Press, looking at the applications of AI and machine learning in the chip verification process. Tune in again next time to hear and learn more about the exciting world of AI.

Siemens Digital Industries Software helps organizations of all sizes digitally transform using software, hardware and services from the Siemens Xcelerator business platform. Siemens’ software and the comprehensive digital twin enable companies to optimize their design, engineering and manufacturing processes to turn today’s ideas into the sustainable products of the future. From chips to entire systems, from product to process, across all industries. Siemens Digital Industries Software – Accelerating transformation.