Complexity: probably the word most associated with new mobility in recent discourse. Complexity is also your friend. I’ll explain why in a bit. Complexity applies to the design of (future) autonomous vehicles and today’s active safety systems, or advanced driver assist systems (ADAS). It applies to manufacturing lines, struggling to manage ramp-up of electric vehicles and the volume production of battery and ePowetrain technologies. It especially applies to the validation, verification and testing of these systems. And it will apply, in the future, to the deployment and utilization of autonomous-electric fleets – the big pot of gold that sits at the end of the mobility rainbow. Some use-cases for these vehicles are obvious, such as fleets of autonomous trucks and delivery vehicles. Others are less clear, such as the multi-function prototypes with reconfigurable interior spaces intended to support evolving business models.
One of the most complex aspects is the development of the semiconductor chips, or integrated circuits (ICs), that will power the compute functions in future autonomous vehicles. These ICs pull in data from the different sensors around the vehicle and, using algorithms for spatial understanding and awareness of surroundings, determine the desired vehicle trajectory and engage the appropriate actuation functions (steering, braking, or a controlled shut down in an emergency) to guide the vehicle. ICs that power this kind of sensor fusion function may have 30 billion transistors and 40 or more layers of silicon, metal and added impurities, called dopants, to create the physical circuitry. This chip may typically be around 100 mm2, with transistors so small you could fit literally thousands of them across the width of a human hair. These chips are also expected to adhere to zero-defect automotive-grade design principles, and operate in harsh conditions up to 150 degrees Celsius. This is all, understandably, quite complex.
Rewind to sometime in the 90s. Typical ICs contain around 275,000 transistors, and the thought of going anywhere near an autonomous vehicle with such chips was beyond consideration. So, a less complex time in IC design, right? Actually, the typical pattern of design back then would be to design the circuits, manufacture them, and then, inevitably, find that they don’t work as intended. Next, try and figure out where the bugs were, redesign the chip, and repeat until a functional IC is produced.
Today, first-pass success of infinitely more complex, AV-ready silicon designs is a viable goal. The difference is, of course, today we have fully automated design, verification and manufacturing readiness flows. In other words, we create a digital twin of the IC, starting with a functional representation of how we want the chip to behave – for example, what to do when the processor receives data from a particular sensor. Then, we build a software model of the chip at an abstract level. This model is verified virtually to ensure the chip functionality meets specification before being translated into a model of the circuitry and tested again for compliance. All of this verification, testing and iteration occurs before the chip is ever physically manufactured. By the time we have a physical chip, the functionality has been tested via billions of verification cycles, and first-pass success is a realistic goal.
Post-manufacturing test of these ICs is now faster, with higher test coverage, and allows us to prove out automotive-grade reliability and functional safety with this being designed-in rather than potential failing units tested-out after fabrication. On-chip self-test technology allows higher reliability, faster test times (test times are a significant cost adder in IC manufacturing) and highly predictable in-field behavior. This is the magic of digital transformation: the conflicting goals of higher reliability and lower development cost become reality.
This change in approach is counter-intuitive: it is now easier than ever to design and build an IC despite increasing chip density and higher transistor count. This is why we see Tesla and other carmakers looking to take control of this increasingly valuable IP, and the software algorithms that run on them. But, how can we continue to lower these investments in time and design resources, increase productivity and design quality, and simultaneously accelerate time-to-market? Well, by leveraging techniques such as high-level synthesis (HLS) for the critical AI logic on a large digital domain-controller SoC.
HLS is how we design the high-level abstract models referred to earlier, allowing design exploration to determine the optimum trade-off between the main three conflicts in IC design: higher compute performance, reduced power consumption (think electric vehicles looking to minimize power consumed by on-board electronics), and surface area of the chip, which directly correlates to overall manufacturing cost. As an example, BOSCH Visiontec used HLS to deliver three new image-processing designs in seven months, even though the specifications evolved over the design cycle. And, BOSCH simultaneously improved the design quality.
HLS takes high-level descriptions of the digital logic functionality in SystemC or C++ and synthesizes them into register-transfer level (RTL) code. Designing at a higher level of abstraction accelerates the completion of initial designs by separating the specification of the chip functionality from the implementation. Designers only need to describe what the chip does, leaving the details of the functionality up to the HLS tool. Using HLS to design at a higher level of abstraction can reduce design times to a few months, and requires half as much code as a traditional design flow. Teams are also more agile at adapting to changes because iterating the design takes a matter of minutes, not hours or days. This is what the digital twin does for IC design, and the principles are the same for everything we create in automotive today.
So, getting back to why complexity is your friend – or to put it another way, your competitive advantage. Complexity in automotive, whether in technology (autonomous, electrification, and mobility services), or process domains (design, manufacture and utilization), offers paths to solving new challenges in ways not possible before. This equates to differentiation and opportunity for everyone in the supply chain. Without complexity, we are left with commodity. The holistic digital twin is the pathway to turning that complexity into competitive advantage at the chip level, the vehicle level, and even at the level of smart cities. All complexity here is interrelated, and having design solutions that blur the boundaries between chip, embedded systems, mechanical systems, manufacturing and utilization is the key. This is exactly what Siemens offers with the Xcelerator portfolio.
The applications and design rules are different between engineering domains. An IC and a vehicle electrical architecture have different design constraints and challenges, but the methodology is the same. Understand the trade-offs and find the optimum design solution virtually, work across domains and co-design electrical, mechanical and software systems, prove it works in a digital format before committing to physical prototypes. And set first-pass success as your goal. Having common data sources, combined with flexible adaptable systems offering real insight via the data, and making this available within an open, modern ecosystem is how we can all turn complexity into a competitive advantage. This is where today meets tomorrow.
To learn more, download our whitepaper Integrated Circuit Design for New Mobility.