Retarget your 2D test to 3D with IJTAG
Design For Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the hard test accessibility (especially for upper dies) and to the high complexity where each die can embed hundreds of IPs. In this paper (see link below) we propose a DFT architecture based on IEEE 1687 to enable the test of 3D stacked ICs. The proposed test architecture allows the test at all 3D fabrication levels: pre-, mid-, and post-bond levels. We present a test pattern retargeting flow using IEEE 1687 languages ICL (Instrument Connectivity Language) and PDL (Procedural Description Language), which allows easy retargeting from 2D (die-level) to 3D (stack-level). Compared to IEEE 1149.1 based 3D test architecture, our proposed 3D test architecture is more flexible and enhances test concurrency without an additional area costs.
See our paper here
Reprinted with permission of IEEE