Master the design and verification of next gen transport: Part Two – high-level synthesis

Excerpt from article: “Master the design and verification of next gen transport: Part Two – high-level synthesis”

Part one of this series outlined advantages of high-level synthesis (HLS) and emulation that next generation transportation designs can exploit. This second part goes into more detail as to how primarily high-level synthesis (HLS) can be used for design exploration and verification.

A high-level definition of HLS’s advantages is that it represents a more efficient abstraction above RTL that is particularly well-suited to (and has been demonstrated in) the types of machine learning (ML) and artificial intelligence (A() designs that are increasingly important toward the delivery of advanced assistance and autonomous driving. Like ML and AI algorithms, HLS uses C++ and SystemC.

Read the entire article on Tech Design Forum originally published on October 2nd, 2019.