Excerpt from article: “Synthesizing Hardware From Software”
In the past, many co-processor solutions have been dogged by communications costs. “There was no good communication protocol between the accelerators that had low enough latency to justify moving the workload from one processing element to another,” points out Nijssen. “If it takes millisecond to move some matrix from one place to another, then the CPU would have been able to complete the task in the same time with less energy due to the time and cost of moving things around.”
“Embedded FPGA is going to be interesting in this space,” says Russell Klein, HLS platform program director at Siemens EDA. “If the FPGA is a separate device, going off-chip to the FPGA might nullify much of the benefit of moving from software to a hardware implementation. Keeping the FPGA on the SoC will mitigate those problems.”
Read the entire article on SemiEngineering originally published on August 22nd, 2019.