Machine Learning Drives High-Level Synthesis Boom

Excerpt from article: “Machine Learning Drives High-Level Synthesis Boom

High-level synthesis (HLS) is experiencing a new wave of popularity, driven by its ability to handle machine-learning matrices and iterative design efforts.

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HLS is a design-automation tool that originally was designed for hardware verification. It uses a higher level of abstraction than RTL and has the potential to reduce design time and verification costs by 25% to 50% overall, according to an estimate from Cadence on the impact of its own HLS product line. Synopsys, Siemens EDA and Xilinx also sell their own HLS packages.

“This is all about how you write a floating-point unit,” said Pratik Mahajan, R&D director for the verification group at Synopsys. “When you use chips for training, maybe you want to use a 16-bit multiplier and a 32-bit adder. Making that decision in C++ is much easier. For one thing, software engineers know it and they can model with a high-level language. At the same time, while high-level synthesis is good in terms of creating the first level of RTL, it is not the best for area and power. This is why people are still hand-coding RTL for complex operations.”

Read the entire article on SemiEngineering originally published on June 6th, 2019.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/hlsdesign-verification/2019/06/06/machine-learning-drives-high-level-synthesis-boom/