Mission-critical applications such as autonomous driving are forcing fundamental changes in the way chips are designed, tested and tracked, from the overall system functionality to the IP that goes into those systems. The robustness of a chip is measured in sigma. Six sigma, the gold standard in manufacturing, is mathematically 1 defect per billion. However designers in chip industry typically design up to 3 sigmas as designing to 6 sigmas for everything would be massively over-designing, trading power, performance, and area, for a financially irrelevant yield gain. Designs of highly replicated components (e.g. SRAM bit cells) are selectively picked for six sigma.
With unlimited time and computing resources, the easiest approach would be to perform Monte Carlo simulations on every single PVT corner. This would ensure that working silicon could be achieved within the desired sigma. However, this is not practical in terms of resources and time to meet time-to-market goals. In order to adapt to the realities of chip-level verification, the typical flow starts out by running a large number of PVT corners to find the worst-cases. These worst-case corners are run through Monte Carlo simulations. While this saves significant time, it still suffers from the possibility that a worst-case PVT at nominal may not be the worst-case at the target sigma. In this event, a true worst case may be overlooked – possibly leading an unexpected failure.
Machine learning techniques can exponentially improve variation-aware design and high sigma verification by delivering unprecedented speed, accuracy, and robust variation coverage necessary for nanometer-scale designs.
For library characterization and validation, ML techniques can significantly reduce standard cell, custom cell, and memory characterization time and resources.
If your goal is to produce high-performance & robust designs fast, then this seminar is a great opportunity to look at two innovative solutions that have pioneered the use of ML techniques to improve design and verification methodologies.
In this seminar, we start with an industry keynote from Amit Gupta – GM for Solido products on use of ML to accelerate electronic design followed by key customer sessions showcasing their experience and benefits of using Mentor’s Solido Variation Designer and ML Characterization Suite
Join us for this lunch seminar and learn how these ML-based solutions uniquely address today’s critical design and verification issues. Sigma and sandwiches on us 🙂