Thought Leadership

What happens in Vegas remains in Vegas but what happens at DAC goes around fast!

By Sumit Vishwakarma

It’s an exciting time for DAC as the conference is coming back to Vegas after 18 years and will definitely draw a large diverse audience from the semiconductor industry. We at Mentor are quite excited for the event as well.  Since last year’s event, we have made several advancements in the Analog Mixed-Signal Verification space and are delighted to share them with the design and verification community.

We have an excellent line up of Analog Mixed-Signal Verification sessions planned for DAC

Featured Sessions in Mentor Booth (#334)

  • June 3, Monday @ 10AM Analog FastSPICE Session: Design activity surrounding 5nm node is quickly ramping, resulting in increasingly complex design issues that must be overcome. Join Greg Curtis, our Sr. Product Manager and learn how Mentor’s Analog FastSPICE® address AMS Circuit Verification challenges at 5nm and beyond. ( Repeat June 4, Tuesday @ 3PM)
  • June 3, Monday @1PM Solido ML Characterization Suite Session: Library characterization done by “brute-force” requires millions to billions of SPICE simulations, and weeks to months of runtime, while verifying the resulting Liberty models is just as difficult. In this live demo Austin Shirley, Application Engineer, will show how MLChar Generator produces production-accurate .LIBs at new PVT corners in minutes, and how MLChar Analytics improves quality of .Libs with fast and comprehensive verification. ( Repeat June 4, Tuesday @ 3PM)
  • June 4, Tuesday @ 10AM Solido Variation Designer Session: At lower nodes, increasing verification coverage and improving design quality is significantly important for fast TTM. In this demo, Mike Sheinin, AE Manager, will cover the latest capabilities in Solido Variation Designer and also introduce Solido’s new High-Sigma Verifier, a next-generation tool with algorithmic breakthroughs that make high-sigma verification faster and easier than ever before. ( Repeat June 5, Wednesday @ 4PM)
  • June 4, Tuesday @ 11AM Symphony Session: 80% of today’s design starts are Mixed-signal designs along with increased design complexity, shorter time to market cycles & increasing need for efficient verification coverage. In this session, Sathish Balasubramanian, Sr Product Manager will introduce Mentor’s new Symphony Mixed-Signal Platform, its performance advantages, intuitive use-model and breakthrough debug capabilities that help achieve first silicon success across several mixed-signal IC applications ( Repeat June 5, Wednesday @ 1PM)

Featured Sessions in Verification Academy booth (#617)

  • June 4, Tuesday @ 3PM Improving Verification throughput: In mixed-signal designs, digital circuits severely slow down the SPICE simulation throughput as they consist of a large number of transistors – much larger than their analog counterparts. In this session, Sathish Balasubramanian, Sr Product Manager will discuss the methodology to improve MS simulation throughput by defining these digital circuits in high-level abstractions during simulations of the whole system.
  • June 5, Monday @2PM RNM Debug Tutorial: Real Number Models (RNM) empowers verification engineer to describe an analog block as a discrete floating point model, and enable it to simulate in a digital solver at near-digital simulation speeds. In this tutorial join Sumit Vishwakarma, AMS Product Manager, and learn how to take advantage of Symphony and Questa Visualizer to debug RNM boundary scenarios in case of a functional failure.

There’s a lot more going on in the booth, so be sure to check out the full schedule and register for sessions here. I hope to see you all at DAC!



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This article first appeared on the Siemens Digital Industries Software blog at