The International Test Conference (ITC) runs from Oct 31- Nov 2 in Fort Worth, Texas. ITC focuses on the electronic test of devices, boards, and systems. Mentor is well represented in the technical program and will be sharing a wealth of knowledge about DFT, BIST, and more. You’ll also find Mentor in booth #301 on the exhibit floor – stop by to hear success stories during customer and partner presentations. Mentor is a proud sponsor of the ART and DATA workshops that immediately follow the conference.
Mixed-Signal DFT & BIST: Trends, Principles, and Solutions
Sunday, Oct 30. 1:00pm
The lack of automated analog DFT means that analog circuitry accounts for almost all failures in automotive mixed-signal ICs. This tutorial reviews trends in ad hoc DFT and fault simulation, essential principles of practical analog BIST, and specification-based structural test.
On Applying Scan-based Structural Test for Designs with Dual-Edge Triggered Flip-Flops
Tuesday, Oct 31. 3:00pm
Several challenges are addressed to achieve the highest structural test quality for designs with dual-edge triggered flip-flops. The experimental results on modified ISCAS-89 and ITC-99 circuits demonstrate the effectiveness of the proposed strategies.
A/MS Benchmark Circuits for Comparing Fault Simulation, DFT, and Test Generation Methods
Tuesday, Oct 31. 4:30pm
This paper describes the first publicly-available A/MS benchmark circuits. These include realistic process models with corners, netlists for common A/MS and digital cells, specifications, and testbenches.
The Emerging Applications of Machine Learning in Testing
Wednesday, Nov 1. 10:30am
Machine learning has been used in data mining and root cause analysis for years, but recent research has broadened its application. In this presentation machine learning applications in testing are discussed and future trends are predicted.
Full-Scan LBIST with Capture-per-Cycle Hybrid Test Points
Wednesday, Nov 1. 3:00pm
This paper presents a novel LBIST scheme addressing test requirements of automotive electronics. The scheme uses pseudorandom test patterns delivered in a test-per-clock fashion in conjunction with per-cycle-driven hybrid test points.
IEEE Analog Test Coverage and Access: A New Study Group for Longstanding Problems
Thursday, Nov 2. 3:00pm
This session features a new standard for analog test access and coverage being developed by a study group for the IEEE Test Technology Standards Committee. Attendees will learn mid-development details of the new standard.