RISC-V summit

I have long contended that embedded software is subject to fashion; every few years something new comes along that everyone is excited about. I am always reluctant to predict what the next thing will be, but six months ago I did risk looking into my crystal ball. It is now looking increasingly like I got it right. This week sees the RISC-V Summit – a technical conference that is focused on everything around these processors. Of course, this year the conference is online.

My colleague Russ Klein and I were chatting about the RISC-V phenomenon and some ideas about how embedded systems might be built differently and we realized that the two subjects of our conversation came together rather well. We decided to propose a session for the RISC-V Summit where we would talk about our new approach to building embedded systems that would be:

• easier to implement
• more power efficient
• very reliable
• hard real time [i.e. fully deterministic]
• very scalable and maintainable
• leverage both hardware and software skills to implement an optimal design

Our session is at 10:15 PST on Thursday 10 December. Here are the full details:

If you would like a copy of our materials, please contact me by email or via social media.

Embedded Software Reimagined: Thread Processors Implemented Using RISC-V

Real-time operating systems enable developers to run a collection of tasks on a system and ensure that real-time requirements are met. As system complexity increases, it becomes more difficult to configure an RTOS to meet all possible operating scenarios. Developers must ensure that priority inversions, deadlocks, resource contention, race conditions, and other timing related problems cannot occur, regardless of the operating conditions of the system. Despite detailed analysis and rigorous verification, many design teams will select a larger and more powerful processor than is really needed to provide a margin of safety against unforeseen circumstances.
An alternative is to assign each task to its own CPU core. This dramatically simplifies many of the scheduling and real-time issues around managing a collection of tasks. With the configurability and efficiency of RISC-V cores it is both possible and practical select and configure a core for a specific task, run just that task on the core, and power it down when the task is not active.
This concept is illustrated using an example design that has both high and low compute complexity tasks, both with and without hard real-time constraints. The selection of the RISC-V core, configuration, and integration into a larger system are covered, as is programming and verification. To address the issue of practicality power, performance, and area (PPA) metrics for the exemplary system implemented in a 14 nm ASIC library are given. This example will be compared to an equivalent system using a traditional RTOS.

If you would like a copy of our materials, please contact me by email or via social media.