Thought Leadership

The height of fashion: RISC-V

By Colin Walls

Having worked in embedded software since before it was called “embedded”, I have spotted a few trends. One of those tends is that the world of embedded software is very fashion conscious. I do not mean that development engineers are wearing the very latest in trendy clothing – I think that is very unlikely! I am referring to the technology trends. Every few years, something else is fashionable – it is “flavor of the month” …

There is a long list of these fashionable technologies. In no particular order: C++, UML, low-power design, Windows CE, Java, Eclipse, USB, Linux, multicore, … the list goes on. The most recent example is the Internet of Things – IoT. In each case, the technology is being talked about everywhere – it is considered to be The Next Big Thing. It is always clear what the current fashion is, because any webinar, article or whatever, is heavily subscribed. I recall presenting a webinar [twice] one evening, on a fashionable topic; I was in front of over 1000 people! After a couple of years, the excitement is tempered and the next one comes along. It is not that these technologies [necessarily] go away, but they find their place in the embedded software world.

So what is next? I am very reluctant to use my crystal ball, as, so commonly, future predictions can look very foolish some years later. But I am feeling reckless today and I will take a risk. The technology that I have seen exponentially increasing in visibility over the past months is – drum roll – RISC-V.

RISC-V is not very new – it has been around a few years – but only lately has it become widely visible. On the surface, it is just a new CPU architecture – there have been a great many of those over the years, some of which never got beyond the data sheet. However, it has some characteristics that make it extremely attractive at this time.

RISC-V is a CPU architecture, but not an implementation. It is freely and readily available for anyone to implement. The architecture is fairly simple, but with great potential for extension and customization. RISC-V is particularly useful for developing multicore systems, which is another increasing trend. There is the possibility to build a Symmetric Multi-Processing [SMP] system using multiple RISC-V cores, as they all have the same architecture. But you have the flexibility for some of the cores to be customized as well. Building an Asymmetric Multi-Processing [AMP] system also makes sense. Each RISC-V core has its own operating system [or none at all], according to its required functionality, with the added benefit that the cores may be customized too. This is considerably more productive than building a system around multiple CPU architectures, where a much greater knowledge base would be needed by the developers.

The embedded software industry’s enthusiasm for RISC-V is manifest in the huge support it is attracting from hardware and software vendors alike. The customizability is a challenge that is readily being met by software development ecosystem provider offerings such as toolchain customization services etc.

A free white paper is available which gives more detail of RISC-V architecture and application. A recent webinar on RISC-V proved extremely popular [remember, I said that was a way to recognize The Next Big Thing] – you can access a recording, including the Q&A, here.


3 thoughts about “The height of fashion: RISC-V
  • You didn’t venture an opinion as to whether or not you thought RISC-v was better. I presume that was deliberate.

    Personally, I very much like the idea of Open Hardware. RISC-V seems relativeLy nascent… perhaps it’s too early to tell how influential it will be.

    I can’t help but think, though, that political situations, and the move away from the usual hardware chip providers, might hasten its advance.

    • @Mark – The term “better” is a little vague and begs the question “Better than what?” I certainly think that RISC-V has some very interesting features technically – in particular, being able to design AMP multicore systems, with customized cores where necessary, in a way that makes software development efficient [only one architecture to support]. A bit of a shake-up with chip providers seems to no bad thing [IMHO] …

      • My apologies if I have misinterpreted your level of enthusiasm.

        I was considering that ‘better’ might be applied to the architecture of RISC-V – that it is potentially customizable for all use-cases using the same tools. I’m not a techie… I merely glean snippets from good people like yourself who take the time to demystify things. Thank you.

        AND that it’s better in the sense that it’s so much more open, so that the brightest and best can move it forward. Newton, who humbly suggested that he merely “stood on the shoulders go giants” also suggested that “we build too many walls, and not enough bridges”.

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This article first appeared on the Siemens Digital Industries Software blog at