CISC and RISC

Some time ago, I wrote about my role as a STEM Ambassador. This has been an interesting experience, giving me the chance to meet various people and connect with others in surprising ways …

STEMNETI got a message from an ex-colleague – an electronics hardware design specialist, who had moved to the other side of the country and had recently become a STEM Ambassador too. Knowing him, I am sure that he is doing a fine job of it. He had received a request for advice on a topic that was more software oriented – not really his area, he felt. He thought of me and his message explained that the topic was RISC and CISC processors – could I help with a few words?

It was not something that I have given much thought to in recent years. It was once considered quite a big deal and I used to enjoy wheeling out the old joke: RISC stands for “Relegate the Important Stuff to the Compiler” [because that is kind of true!]. I wrote up my thoughts and he seemed happy with them. I thought that it might be interesting to share them here:

Although less widely discussed nowadays, for many years there has been a categorization of CPUs as being Complex Instruction Set Computers [CISC] or Reduced Instruction Set Computers [RISC]. A CISC machine has a large instruction set, so that compiled code is quite compact, as each instruction does quite a lot of work. This reduces the memory image size for a program of given complexity, but each instruction may take many clock cycles to execute. On the other had, a RISC device has many fewer instructions available and each one does a simple job. The code size is, therefore larger, but each instruction takes less time, commonly just one cycle, to execute. The choice between CISC and RISC is therefor a complex trade-off between a number of factors:

  • memory usage
  • execution time
  • CPU complexity [and, hence, size and power consumption of the chip]

Many early computers were RISC, as the technology was not there to do more complex things. In due course, both architectures persisted and were developed in various ways. With minicomputers in the 1970s, RISC was initially prevalent. A PDP-8, for example had a very simple instruction set with a single register [accumulator] and no stack. Some instructions could be “overlaid” to save memory – a single instruction might have several bits, each of which activated a specific functionality. The later PDP-11 was much more CISC, with a very flexible instruction set, where any just about operation could be performed on a register, the location pointed to by a register or an absolute memory location.

As embedded systems increased in complexity and, thus, needed 32-bit CPUs, an initial favorite was the Motorola 68000 family. These chips were very clearly CISC, having an instruction set uncannily like the PDP-11. Later, it was superseded by ColdFire, which had a compatible instruction set, but was supposed to be a RISC architecture. PowerPC was also introduced and described as RISC, even though it had more instructions than a 1960s mainframe.

Over the years, various CPU architectures came an went: i960 [RISC], i860 [CISC], 29K [RISC], SPARC [RISC], 88K [CISC]. Now the dominant CPU architecture for embedded – at the higher end anyway – is ARM, which is always described as RISC. Other players are x86 [CISC] and MIPS [RISC].

Nowadays, one hears little discussion about whether a particular CPU is RISC or CISC and no debate about which is best. Different CPU architectures are assessed by their own strengths and weaknesses, with RISC/CISC being seen as a continuum instead of a choice.

Comments

4 thoughts on “CISC and RISC
  • Roger Sundman

    A very well balanced article and the discussion about RISC and CISC will perhaps never end.

  • Jani Launonen

    Nice article. I’d like to point out that RISC was also reaction to the fact that compilers could not really make good use of complex instructions at the time and most fancy instructions were just unused in CISC (except for hand assembly).

    Also, sometimes the difference between the RISC and CISC is considered to be the Load-Store architecture (or register-register ops.) versus memory-register operations and/or complex memory addressing schemes.

    One final interesting thing is the RISC-V – an open RISC “standard” which has some interesting expansion possibilities thought out from the start. It could be that in few years one can have embedded systems based on RISC-V processor on desk. That would be interesting.

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