Via modeling – what do I really need?

The whole via simulation issue is admittedly complicated, and I think really boils down to whether the vias are single-ended or differential, and at what speeds you are running.
When the vias are differential, the return current is basically self-contained around the vias since they have equal but opposite signals on them. Because of this, the built-in analytical model in HyperLynx models differential vias well into the multi-GHz range, and are suitable for most SERDES busses like PCI Express. We have, however, enhanced our via modeling in HyperLynx 8.2 to integrate with our 3D field solver. Now you can create highly accurate via models up into the tens of GHz range, with the ease of HyperLynx.
Single-ended signals, on the other hand, rely on the PDN (mainly stitching vias and/or stitching capacitors) for their return current path. So, our PI-integrated via models are most relevant for fast, single-ended signals (like DDR3).
We have a via model for every need. Vias are more complicated to model than traces, so there will always be a tradeoff between simulation accuracy and speed, and it is important to use the via model best suited to your application.
To read more about via modeling take a peek at my recent article in PCDandF:
http://pcdandf.com/cms/component/content/article/171-current-issue/8439-designers-notebook