The new VX.2.12 release of HyperLynx delivers state of the art simulation capabilities to mainstream designers by combining advanced modeling and simulation techniques with automated workflows that guide users through analysis step by step. In VX.2.12 improvements have been made across the following areas:
- DDR interface design & verification
- Serial channel design & verification
- Power Delivery Network (PDN) design & verification
- HyperLynx Apps
- HyperLynx Advanced Solvers
- HyperLynx DRC
- General Improvements
DDR interface design & verification
Hyperlynx offers full workflows for both pre-layout design exploration and post-route verification of DDR-based interfaces.
New in VX.2.12 is the ability to simulate and plot DDR5 eye diagrams down to a probability of 1e-16 in both batch and interactive simulations. This accurately models rise/fall asymmetry, works with AMI models & Tx/Rx jitter specs, runs simulations in seconds, works with crosstalk analysis, and produces eyes plot with probabilities shown in color. This allows system operating to be measured in compliance with the DDR5 spec.
HyperLynx VX.2.12 also has the ability to adjust controller output timing for Command/Address signals to improve DRAM timing margins. CA / CS adjustments at either the class level or individual bit level. This allows HyperLynx to accurately model the adaptive timing capabilities of modern DDR controllers.
Serial channel design & verification
Hyperlynx VX.2.12 can analyze serial links for compliance with 210 different serial link protocols and variants. This release adds the ability to run SerDes Compliance Analysis for links supplied as S-parameter files. Designers can now leverage HyperLynx’s extensive protocol support to analyze channel models derived from measurement and other modeling tools.
Compliance analysis for IEEE/OIF 112Gb/s has been updated to include Vertical Eye Closure (VEC) / Vertical Eye Opening (VEO) measurements that are now part of the standard. This improves measurements for closed eyes and produces a plot of the vertical cross-section of integrated eye diagram.
Power Delivery Network (PDN) design & verification
Modeling of sink pins during DC Drop analysis has been updated to make the equipotential area of the sink smaller. This produces more accurate current distributions for large pins with thermal reliefs predicted more realistically.
HyperLynx Apps are changing the game in signal and power integrity by making analysis accessible to mainstream engineers. It’s now possible to run HyperLynx Apps without having a Station license, providing you have the necessary HyperLynx licenses.
The DC Drop, Loop Inductance and SerDes Compliance App have been improved in 2.12 to make one-button simulation with HyperLynx Apps easier and more accurate than ever.
HyperLynx Advanced Solvers
Port de-embedding has been improved so that the 3D areas used to model vias, IC/connector breakouts and blocking capacitors in serial channels can be smaller and solve faster, without compromising accuracy. Automated port creation for large connectors has also been improved. 3D area naming has been improved through the user of hash tags, which reduces the number of unique areas that need to be solved and improves overall analysis run time.
HyperLynx Job Distribution allows 3D EM simulations to be run in parallel to increase solver performance, supporting several different parallel computing schemes. In one recent benchmark, 116 3D simulations were run using 14 solvers in parallel, utilizing a total of 112 cores and achieving 85% of maximum theoretical computing efficiency, even through the user’s computer was 3000 miles away from the data center where the jobs were running.
The DRC DDR wizard automatically recognizes DDR interfaces in a design and configures DDR-based rules for signal quality and timing checks based on the design’s unique characteristics. The DRC DDR wizard has been upgraded in VX.2.12 to DDR interface checking quicker and easier.
Two new high-speed signal integrity rules automate signal quality checking for sensitive nets and help ensure that reference nets are copied accurately when a group of nets require identical routing.
Load times for larger designs are reduced by creating a simulation-optimized version of the design database (.odm file). This file is created automatically on first load and updated when the design file changes. Use of the .odm file cuts typically loads times in half or better.
Xcelerator Share lets HyperLynx users publish simulation results in the cloud to increase efficiency and collaboration across the organization.
HyperLynx workshops get you up and running quickly by guiding you through HyperLynx workflows, providing databases and models, instructional videos and step by step instructions. HyperLynx workshops can be downloaded 24/7 from Support Center.
With new features and enhancements across the VX.2.12 release, HyperLynx helps you create, verify, and optimize your designs quicker than ever before. Download the release today!