There have been times, when designing a board, that I had an uneasy feeling in the pit of my stomach. I had a sinking feeling that the DDR subsection wouldn’t work as expected during bringup, and my boss would come by every half an hour asking if I needed any “help” (no pressure, of course). And there’d be the firmware guys snickering in the background. Stuff that nerd nightmares are made of.
Oftentimes, the problem was that the board stackup and space just wouldn’t allow me to follow the guidelines. Other times, the guidelines themselves were vague. Nothing much I could do about either.
In our latest webinar from the HyperLynx team at Mentor Graphics, Min Maung tackles these concerns by going through an overall flow of simulating the parallel DDRx bus to give designs the best chance of working right the first time. You can view the presentation here.
In it, he discusses a full range of topics including:
- Fundamentals of the DDRx bus
- Analyzing which topologies will work for you before getting layout started
- Generating the required board constraints for your design
- Validating your board after you have a layout to work with
- How to debug your design if you find issues during simulations
In addition to the invaluable information provided during the presentation, several pertinent questions were asked by the audience after the presentation. These included questions regarding:
- How to incorporate 3-D structures in DDRx simulations
- How Leveling timing can be analyzed
- How to simulate the effects of power planes during simulation
…and many more.
To get answers to these and other such DDRx related questions, and engage in the ensuing discussion, head over to our Community Discussion page here.