DDR Designs for Today and Tomorrow

It used to be that only specialized products had high-resolution displays or network connectivity. Today, even your thermostat and the fitness tracker on your wrist have advanced graphics and wireless connectivity.

To enable these features, engineers need to add memory to pair up with the advanced processing that’s propelling us to the future. So, if you need to add memory, commonly the DDR variant, to your design, that seems like a straightforward task, right? Just connect the controller to the memory devices in your schematic and call it done…

If only it were that easy! The real challenges start after schematic creation. Do you used a balanced-T route between the controller and DRAM or fly-by? Will you meet system-level timing requirements? Do you need termination resistors and, if so, what value do you choose?

The unfortunate reality is that the DDR memory interface is one of the most complicated modern busses.

The address/command signals have a timing relationship with the main CLK signal while the data bus (byte lanes, DQ) has a timing relationship with the data strobe (DQS). Challengingly, there’s also a timing relationship between the DQS and the CLK that has to be maintained at all DRAM ICs (0.25 cycle).

The address/command bus and the data bus also use different termination approaches; the data bus is typically terminated with On-Die-Termination inside the controller/DRAM (starting with DDR2), while the address/command bus needs external termination, typically Thevenin-style but sometimes series and parallel.

Rules of thumb and reference designs only get you started. The reality is, every design is different. Engineers need confidence that their DDR design will work and meet all specs.

With PADS HyperLynx DDR, a built-in wizard lets you easily set up DDR Signal Integrity and Timing simulations. The wizard gives you pass/fail results per JEDEC specs and an interactive HTML-based report lets you drill down to get details on where your design is failing. Simulation data can be saved so that you can explore and examine critical nets in the interactive oscilloscope viewer as well.

Designing modern products with advanced technology like DDR memory requires a modern approach. Embrace the future with open arms and use the PADS HyperLynx DDRx Wizard, a key component of the PADS Product Creation Platform, to tackle your next DDR design.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/electronic-systems-design/2016/10/17/ddr-designs-for-today-and-tomorrow/