Functional Safety Whitepaper: Developing Safety Architectures for AI Accelerators
AI accelerator chips such as NPUs and GPUs are increasingly used in safety‑critical systems, but their massively parallel architectures (simplified in Fig1.below) challenge traditional functional safety techniques.
Our new whitepaper, “Developing Safety Architecture for AI Accelerators” examines why approaches like lockstep processing and periodic software tests are impractical for AI accelerators, and explores alternative, architecture‑aware safety strategies. It highlights how inherent parallelism can be leveraged through selective redundancy, statistical monitoring, and graceful degradation. The paper also presents Siemens’ model‑based methodology, using high‑level and RTL models combined with quantitative evaluation on the Veloce emulation platform, to design and validate robust safety architectures without sacrificing performance or power efficiency.
Interested in a deeper discussion on our Functional Safety expertise and offerings? Feel free to contact your local Siemens representative to arrange a more detailed technical session!
About the Author
Ken Boorom earned both BS and MS degrees from Stanford University and has worked in integrated circuit design for 26 years. Since 2015, Ken has been an active member of the ISO 26262 standards committee, contributing to the development of automotive functional safety standards. With numerous publications and patents, Ken brings deep expertise in IC design, safety analysis, and industry best practices.
