Enhancing SRAM Yield Prediction with Solido’s AI-Powered Technologies
In the ever-evolving world of semiconductor technology, predicting and enhancing the yield of Static Random Access Memory (SRAM) has always been a critical challenge. Our latest white paper, co-authored with GlobalFoundries, delves into a novel methodology that leverages AI to predict SRAM yield more accurately, even in the presence of rare random defects.
Introduction to the Challenge
SRAM is a fundamental component in modern electronics, known for its speed and reliability. However, as we push the boundaries of technology with smaller bitcell footprints and higher performance demands, unexpected yield degradations can occur. During the development of a high-performance, high-density 6T SRAM bitcell on GlobalFoundries’ 12nm technology, we encountered such a challenge. The root cause was traced to a rare but random defect affecting the NFET devices within the SRAM bitcell.
Understanding SRAM Failures
SRAM failures can be broadly classified into two categories: Hard Fails and Soft Fails. Hard Fails are typically due to catastrophic physical defects, while Soft Fails are linked to intrinsic device variability and are often voltage-sensitive. One common Soft Fail is the Access Disturb Fail, where the data stored in a bitcell is erroneously flipped during a read operation. This type of failure becomes more pronounced when NFETs are stronger and PFETs are weaker than their target specifications.
The Novel Prediction Methodology
Our white paper introduces a groundbreaking approach to include rare random defects into yield prediction frameworks using the Solido Design Environment (Solido DE) software. By simulating the impact of these defects on the threshold voltage (Vt) of NFETs, we can predict the minimum operating voltage (Vmin) with greater accuracy.
Steps to Accurate Prediction
Data Collection and Analysis: We began by collecting extensive data from silicon wafers, including threshold voltages and functional yield testing results. This data revealed that the wafers were Read Fail limited due to weaker PFETs.
Simulation Setup: Using SPICE simulation testbenches, we simulated Read Fail scenarios and adjusted the models to match the observed Vt data. These simulations were run in Solido DE, leveraging its High-Sigma Verifier tool to find the fail-sigma of the circuit at various voltages.
Defect Modeling: To account for the rare random defects, we introduced an additional variable in the device models to degrade the NFET threshold voltage. This variable was adjusted to match the observed defect distribution, resulting in a more accurate prediction of fail-counts.
Validation: The predicted fail-counts were then compared to the silicon data, showing a much smaller gap between predicted and observed Vmin. This validation confirmed the effectiveness of our methodology.
AI-Powered Efficiency
One of the standout features of our approach is the use of AI technology within Solido DE. High-Sigma Verifier significantly speeds up variation-aware high-sigma verification, allowing us to achieve SPICE-accurate results in a fraction of run time compared to traditional brute-force methods.
Conclusion
Our collaborative effort with GlobalFoundries has resulted in a robust methodology that enhances the accuracy of SRAM yield predictions, even in the presence of rare random defects. This advancement not only improves the reliability of SRAM products but also paves the way for more efficient and effective semiconductor manufacturing processes.
We invite you to read the full white paper for a detailed exploration of our methodology and its implications for the future of SRAM technology.
Acknowledgments: Thanks to Sandeep Puri of GlobalFoundries and Mohamed Atoua of Siemens EDA for working on this paper.
