Redefining High-Sigma Verification: Reflections on Presenting AI-Powered Methodologies at DAC 2024
This year, I had the privilege of presenting at the 2024 Design Automation Conference (DAC), which took place in San Francisco, California. DAC has always been a hub for innovation, offering the opportunity for engineers, developers, and industry leaders to showcase advancements that push the boundaries of chip design and electronic systems. It was a perfect stage for my co-presenter, Chengcheng Liu from Nvidia, and me to introduce our work titled “AI-powered high-sigma verification methodology for standard cells.“
As chip designs scale, relying on Monte Carlo simulations and past experiences to predict worst-case Process, Voltage, and Temperature (PVT) corners often proves unreliable. Our presentation introduced an AI-driven, automated methodology, leveraging Siemens’ Solido Design Environment. Solido PVTMC Verifier and Solido High-Sigma Verifier, used by NVIDIA engineering team, demonstrated unprecedented improvements in both accuracy and runtime.
One key highlight was our work with latch-based D flip-flop circuits, where Solido High-Sigma Verifier achieved a 2,500,000X runtime improvement over traditional brute-force methods, verifying failure modes with only 4,000 simulations. Additionally, we achieved 6.322 sigma verification for target cells, with a 30X speedup in runtime.
To learn more about Solido Design Environment technologies, visit https://eda.sw.siemens.com/en-US/ic/solido/design-environment/
