A few months ago, it was reported that Apple was beginning the development of their A19 Bionic SoC using a 2nm process Apple A19 Bionic. While the current A17 Bionic is anticipated to have about 20-24 billion transistors, it is projected that the A19 Bionic will have even more! As modern System-on-Chips (SoCs) become larger and more complex, design IPs have become essential building blocks.
Design IPs allow for modularization and re-use of design components, which is crucial for managing the increasing scale and complexity of SoCs. However, IP data libraries can be vast and contain multiple views and formats, leading to potential inconsistencies that may be difficult to identify. That is why a robust QA framework for design IPs, which can detect inconsistencies early in the flow, is a crucial component for successful silicon production.
A robust IP QA framework should possess the following capabilities:
Design- and technology-agnostic IP QA: The framework should focus on identifying issues early in the flow, regardless of the underlying design methodology or technology node being used.
Comprehensive validation coverage: The validation methodology should cover a wide range of checks to ensure thorough verification.
Adaptability to changing specifications: Performance and specifications may change at each revision made to the design IP. Therefore, the QA methodology must have the ability adapt to these changes.
Flexibility for adding functionality: To support a wide range of use cases, the QA methodology should be extensible, and allow for the addition of custom functionality to complement existing built-in checks.
Implementing a proper QA methodology can ensure that critical metrics such as consistency, accuracy, and completeness are met, leading to better silicon quality and shorter production schedules. I delivered a webinar presentation on how Siemens EDA’s Solido Crosscheck addresses IP QA challenges in the semiconductor industry. If you missed it, I encourage you to watch the on-demand recording available here : Masterclass – IP QA best practices