What’s New in Z-planner V2023.1

By Don Kost

Z-planner Introduction

Creating the correct stackup using the proper materials and then transferring that information to your fabricator is extremely important in the success of your PCB design.  Being able to “left shift” this stage of your design process can add huge cost and quality savings into your entire design.

Z-planner V2023.1 builds on previous versions by enhancing rigid/flex useability, tighter integration with Xpedition and HyperLynx and the addition of more Mil-Aero materials to the dielectric materials library.

So, let’s look at some of these new enhancements in more detail.

Stack up Wizard Enhancements

There were a couple changes made to the Stackup wizard too.

The biggest enhancement is the addition of adding via definitions. This allows the extra plating layers needed for sequential lamination designs to be added before the impedance calculations are done.

A usability enhancement was added to assign a frequency for the impedance planning. Impedance settings are now remembered for later use in the stack up editor.

Stackup drill wizard
New step added to the stackup wizard – Drill definition

Via Drill Table

An updated drill table has now been added to the viewer as well as the Excel export spreadsheet.

The new drill table has updated graphics for a more detailed description of the vias being used.

Drill table export to excel
Drill table from the viewer or excel export


There were several updates with the integration other tools. Let’s look at them separately.


You can now import the percent copper data from Xpedition. Using this data, you get more accurate results of the impedance calculations since the actual prepreg thickness can be calculated.

Import and Export data from Xpedition


The etch factor calculation now uses the same formula as HyperLynx.

etchback stackup calculations

Proposed definitions of “etchback” and “etch factor,” where x (etchback) is the difference between w1 and w2, and etch factor is defined as the degree of etchback per thickness.

HyperLynx Advanced Solvers:

Stack up data from HLAS can now be directly imported.

This addition continues to improve the integration with the Siemens EDA flow.

Hyperlynx field solver


  • Rigid and flex import/export with LineSim
  • Rigid import/export with to BoardSim
  • Rigid import/export with HyperLynx Advanced Solvers
  • Import Add in v 2023.1


  • Rigid and flex import/export with Valor NPI


  • Rigid and flex import/export with Xpedition

Polar Instruments:

Support to import/export Polar .stkx files was added. Now all major PCB stack up formats are now supported.

export to Polar Instruments
Polar Instruments .stkx Import and Export


IPC2581 is a widely used stack up format by EDA tools, now the latest version of IPC2581 – the C version is supported by Z-planner Enterprise. This version now supports all versions of IPC-2581.

IPC 2581C Import and Export
IPC 2581C Import and Export

Sequential Laminations in Z-solver

A sequentially laminated stripline tab was added to the Z-solver tab to support the buildup process.

Sequential lamination supports a more explicit editing on the dielectric properties for build-up process. 2-ply prepregs top/bottom is also supported to a new added “sequentially laminated stripline” tab.

Sequentially Laminated Stripline added
dual-ply top and bottom, single ended and differential as well as coplanar and differential coplanar
Z-planner Enterprise supports all commonly used impedance structures. Including Dual-ply Top/Bottom, Dual-ply Top, and Dual-ply Bottom for Single-ended, Differential, Single-ended Coplanar and Differential Coplanar.

Via Plating DFM Checks

These new checks were added:

  • Vias should be symmetrical.
  • Vias require plating on outer layers.
  • Plating should be on the outer side of copper layers.
  • For blind and buried vias, prepregs are required on the outer side of via plating.
New Stackup Via Drill validations
New Via/Drill validations within the stackup DFX Settings

Library Updates

Resin Type:

A resin type column is added to the DML. A wide range of known resin systems are available with readily identifiable chemical structures.

PCB Dielectric resin type sorted by Tg
Dielectric Resin type can be sorted by Tg value

Low-Dk Glass Filter:

A “Low Dk Glass” filter is added to the DML. Each laminate manufacturer uses their own nomenclature for low-Dk glasses, to help mitigating the glass-weave skew.

26 Low-Dk (and Low-Df) Glass Laminates have been added in v2023.1. No other Stack up Software has all these materials.

selection of E-glass laminates with their corresponding low-Dk glass version in the Z-planner Enterprise library.

Selection of E-glass laminates with their corresponding low-Dk glass version in the Z-planner Enterprise library.

E-glass vs Low-Dk glass

Dk=6.8 vs Dk=4~5

Laminate nomenclature

  • Each laminate manufacture use their own nomenclature for low-Dk glass
  • EMC, Nanya, and Panasonic use “K”
  • Doosan and Shengyi use “N”
  • AGC-Nelco uses “SI”* and TUC uses “SP”

Price premium

  • ~ 50-70% cost increase per bare board

Copper Roughness:

Copper roughness is another important factor that impacts the insertion loss for high-speed design. Now, the copper roughness data has been added to the library. This will provide more accurate loss calculation for various stackups.

prepreg side of trace is textured by the copper foil maker
  • Prepreg side of trace is textured by the copper foil maker, plus…
  • The PCB shop applies an oxide coating to top and side surfaces to maintain bond strength – Rougher surface = stronger bond

Z-planner Enterprise contains detailed information on both laminate side and prepreg side copper roughness. It is the only software tool that manages, tracks and models copper roughness and loss on both sides of copper foils.

High Speed Materials

As always, updates are continuing to keep the library materials up-to-date and adopt new materials. For this release 27 new high-speed materials are added.

 Materials are constantly being updated and currently there are 235 material families in the library.

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This article first appeared on the Siemens Digital Industries Software blog at