By Stephen Pateras, Mentor Graphics Two DFT-related rules for success are as true today as they were 30 years ago
By Rick Fisette, Mentor Graphics Remove ATPG from the critical path to tapeout with hierarchical DFT plus test pattern retargeting…
By Geir Eide, Mentor Graphics What to know about today’s scan diagnosis and yield analysis technologies…
By Geir Eide and Jonathan Muirhead Analyzing fail data with pattern matching helps companies identify yield limiters faster to increase…
By Ron Press, Mentor Graphics Try Hybrid ATPG and LBIST when you need both in-system test and advanced fault detection.
By Rahul Singhal, Mentor Graphics Near-zero defect testing for safety-critical ICs means also testing the DFT logic.
By Martin Keim, Mentor Graphics What’s new in 3D IC testing? This summary from an ISTFA tutorial has the answers
By Ron Press, Mentor Graphics DFT with less risk to your design flow? Here’s how.
Retarget your 2D test to 3D with IJTAG
