A new logic built-in-self-test (LBIST) technology significantly improves cycle time for in-system tests of automotive devices.
As cars become ever more computerized and rapidly adopt advanced safety functions, the demand for more complex safety-critical components is growing. The ICs designed for use in advanced driver assistance systems or autonomous vehicles must meet stringent quality and long-term reliability requirements. Not only do the ICs for safety-critical applications need high-quality manufacturing test, but they need robust in-system test to ensure reliability for the duration of the device lifespan. Adopting test solutions that address challenges posed by automotive electronics is an essential step for any company competing in the automotive electronics space.
One test solution for in-system and in-field test of automotive ICs is a scan-based logic built-in-self-test (LBIST) scheme that optimizes test time and area overhead. This scheme was presented by Nilanjan Mukherjee at the 2019 International Test Conference. He summarizes that presentation in this 10-minute video:
In the video, Mukherjee, a senior engineering director for the Tessent product family, describes how the proposed scheme works with observation test points that capture faulty effects every shift cycle into separate observation scan chains. This new scheme is behind the “Logic BIST – Observation Scan Technology (LBIST-OST)” available as part of Tessent Logic BIST product.
In the observation scan architecture, an LFSM on the input side operates as a decompressor in ATPG, and as a pseudo-random pattern generator in LBIST mode. On the output side, a spatial compactor drives channel pins during ATPG, and drives the MISR in LBIST mode.
Control and observe points (test points) are needed for LBIST to improve random-patterns test coverage. In observation scan, the observe points are connected in separate chains, which lets them capture circuit responses not just during a capture cycle, but also during the shift cycles. In traditional LBIST, there are multiple shift cycles before a capture cycle and therefore observing circuit responses during shift improves the overall observability of the design. To reduce the complexity of fault simulation, the observe points only observe test responses, and provide no test stimuli to the gates.
Mukherjee describes how the observation scan cell mode is controlled and shows the fault simulation process for regular scan and observation scan. LBIST simulation can be distributed, speeding up the process. He wraps up by reviewing some experimental results obtained for contemporary automotive designs that demonstrate the feasibility and benefits of the proposed BIST scheme. The test pattern count to reach 90% coverage is reduced by 9x on average with the use of observation scan, which directly translates to test application time savings.
For ICs that need to meet ISO 26262 and achieve ASIL D certification, in-system test is a requirement. Designers can improve in-system test time and reduce area overhead using LBIST with observation scan. Observation scan completes tests faster, thereby simplifying key-on, key-off, and periodic checkups during functional operation.
Watch the video Test Time and Area Optimized BIST Scheme for Automotive ICs