The rapid development of advanced driver assistance systems and autonomous vehicles has grabbed the world’s attention and imagination. While true autonomous driving is still many years off, the promise of incremental advances in driver assistance systems is of immediate concern to the entire automotive supply chain from OEMs to IC designers. In response, we see very fast development of the technology needed to enable all levels of autonomous operations for cars and trucks…
This was the topic of a keynote address at the 2019 ITC India presented by industry luminary and IEEE Fellow Janusz Rajski, the VP of engineering for the Tessent DFT and Yield division of Mentor, a Siemens Business.
The rapid growth in the market for automotive ICs stems from the demand for massive amounts of computing power needed for advanced driver assistance. These systems must process the huge volume of data generated by the sensors and actuators in real time.
These complex safety-critical electronics present notable challenges regarding the requirements for extremely high quality and long-term reliability. The high-performance requirement is driving designers to adopt advanced technology nodes faster than ever. The new technologies come with new defects mechanisms and therefore risks, which must be prevented, detected, and repaired before the chips even go to market.
New silicon test technologies that help meet the high-quality manufacturing and in-system test requirements are being adopted at an accelerated rate. Rajski reviewed the challenges and the new innovations in DFT and test technology in his keynote, particularly regarding meeting the high-quality requirements defined by the ISO 26262 standard with improved manufacturing test and in-system test.
High-quality manufacturing test for automotive ICs is facing challenges because of the move to smaller process geometries and larger designs. There are newer methods that are very effective at finding a significantly larger percentage of the defects in a device, whether in the interconnect or inside the standard cells. This is an important distinction for devices that use FinFET transistors. Using this cell-aware test greatly improves defect detection. We’ve seen innovations that improve analog/mixed-signal test as well, particularly in the area of automation around evaluating existing analog tests so you can eliminate those that are not useful and generate new ones that are.
In-system test helps ensure the reliability of an electronic system by performing periodic testing during the functional operation of the system. Traditional built-in-self test isn’t sufficient because they don’t reach all on-chip test resources or perform on-line test diagnosis. Mentor offers the Tessent MissionMode controller to provide system-level low latency access to all IJTAG-compliant on-chip test IP.
If you missed Rajski’s keynote, you can still read about how Mentor addresses DFT for meeting ISO 26262 requirements in this whitepaper