SEMICON West is happening this week, again at the Moscone Center in San Francisco. SEMICON West seems to grow in variety and size each year, and there is something there for everyone in the electronics supply chain.
Co-located with SEMICON West is the Test Vision Symposium, which holds sessions on Wednesday, July 10 and Thursday, July 11. This is where the latest ground-breaking advancements in IC test are being discussed. It has keynotes, panel sessions, poster sessions, and papers that focus on industry trends, challenges, and solutions facing the test community.
One paper, presented by Mentor’s Matthew Knowles, presents a new way to accelerate silicon bring up. Mentor developed a new tool that connects the test software with the ATE through an industry-standard interface. Mentor’s tool supports BOTH Teradyne and Advantest support, with more to come in the future.
This connection between DFT software and ATE hardware all but eliminates the traditional iterations between the DFT tool and the ATE during debug and bring up. The results so far are stunning; months of effort in first silicon bring-up are reduced to a week.
If you aren’t at SEMICON West this week, have no fear – you can still learn more about the technology in this free whitepaper, Accelerating test pattern bring-up for rapid first silicon debug