Use bench-top ATPG bring-up to better understand and interact with silicon bring-up test data and reduce silicon bring-up cycle time. This 12 minute video demonstration of Tessent SiliconInsight shows you how.
To reduce silicon bring-up costs and significantly speed up diagnosis of the root cause of IC test pattern failures, consider updating to a software-based benchtop system. To learn about using the Tessent system for benchtop test, diagnosis, and characterization of digital ICs containing design-for-test (DFT) structures such as scan and on-chip compression, watch this 12-minute on-demand seminar (see link below)
Larger designs and smaller feature sizes create challenges along the entire IC design and test flow, including in physical failure analysis (PFA). The diagnosis process typically involves time consuming and costly roundtrip between PFA, test, and DFT engineers and access to ATE machines for silicon bring up. But this new software-led flow speeds silicon bring-up within the Tessent environment.
The Tessent SiliconInsight system includes a computer connected to a bring-up/validation board with the device under test (DUT). Comparable commercially available setups have until now have been limited to built-in self-test (BIST) and other test instruments accessed exclusively through the DUT’s JTAG port. With this new system, the scope is expanded to non-JTAG test access and a much wider range of pattern applications and diagnosis routines. For instance, ATPG patterns with-chip compression and over 25 external scan channels can be tested and diagnosed at the push of a button.
The benefits of using the Tessent benchtop system include lower silicon bring-up costs and significantly quicker diagnosis of the root cause of test pattern failures.
What you will learn in the free Tessent seminar:
• What’s required to debug, diagnose, and interact with DFT structures in digital ICs such as on-chip compression, scan/ATPG, Built-in Self-Test (BIST), and IEEE 1687 IJTAG.
• Software technology that simplifies and automates the process of generating dedicated diagnosis patterns and mapping of results to internal registers.
• Enabling a high-availability benchtop test and debug environment for digital ICs.