SDC verification as a first-class asset: A deep dive with Chandu Challapalli
Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-Based Timing-Intent Verification with Questa One, Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle. Learn how Questa One brings structure and automation to timing-intent verification—helping teams achieve faster signoff and greater confidence in first-pass silicon success.
Key Discussion Points
- Why timing constraints matter: How SDC files capture design intent—and why ignoring their verification invites silicon risk.
- What is timing-intent verification?: A clear explanation of validating clocks, exceptions, and constraints against real design behavior.
- Finding the right balance: The hidden costs of under-constraining versus over-constraining timing.
- Common SDC pitfalls: Missing clocks, invalid exceptions, and legacy constraints that mask real bugs.
- Shifting left on timing: Why verifying constraints early—alongside RTL—reduces late-stage surprises.
- What’s next: A glimpse into continuous, AI-assisted timing-intent verification and tighter frontend/backend alignment.
Bugged Out
Every chip has bugs — the real question is how fast you can find and fix them. Bugged Out is the bite-sized podcast where we shine a light on the art (and science) of functional verification.
In just 10–15 minutes per episode, host Harry Foster, Chief Scientist, Verification, Siemens EDA, sits down with leading innovators, engineers, and researchers to talk about what’s shaping the future of verification — from AI-driven tools to design-for-test, coverage closure, reliability, and more. Expect candid conversations, practical insights, and a few “war stories” from the trenches of debug.
Whether you’re a verification engineer, a design lead, or simply curious about how we “get the bugs out” of the chips that power our world, Bugged Out delivers focused, informative conversations designed to fit your busy schedule.
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