What’s New in HyperLynx VX.2.3?

I’m glad you asked! HyperLynx® VX.2.3 contains a large number of signal- and power-integrity analysis features, with a big focus on SERDES channel design and analysis (2-minute video). The release also includes more than 40 customer-requested enhancements (Ideas). Major new functionality is listed below.

Automatic Channel Extraction and Modeling (Industry First)

In VX.2.3, HyperLynx automatically identifies which parts of the net need to be modeled in a 3D vs. 2D field solver. The channel is divided automatically, with each part modeled in the respective field solver and then recombined to form the interconnect. The over-arching model can then be used for subsequent time- or frequency-domain analysis. This is an industry first! No other tool has such built-in intelligence.

The automatic process ensures return path continuity, avoids double counting of trace segments, and implements structure-specific port creation, # of mesh elements, and so on. It also reduces the time between design revisions because the 3D field solver can be run by a different team (the RF team, for example) than the team performing the PCB design. Additionally, once the S-parameter model is generated it can be automatically reused for different instances of the same 3D structure. 16-minute webinar

Explore the solution space and optimize 3D structures (3D Explorer)

Save time and effort when exploring the solution space and optimizing 3D structures. With the HyperLynx 3D Explorer, you don’t have to start from scratch because you have access to templates of commonly used 3D structures, whose parameter values can be specified and swept. You can also import structures from previously routed designs, parameterize, and sweep to optimize them as per the data rate, protocol, crosstalk requirements, jitter, BER, EMI, and more. Video (2:30 mins)

Protocol-specific channel compliance verification (SERDES Wizard)

With the SERDES wizard, you can perform protocol-specific channel compliance verification for more than 25 SERDES protocols such as PCI Express®, Ethernet®, and so on, simply by selecting the net and picking the required protocol. Using built-in protocol-compliant, buffer and package models, you can validate the overall interconnect without having to depend on complex IBIS-AMI models. You can eliminate the trial-and-error approach and perform equalization optimization using reference protocol architecture, while imposing constraints such as DFE, FFE, and CTLE. Video coming soon!

Perform SI and crosstalk analysis on multiple signal nets (General SI Batch Wizard)

Identify signal integrity issues using batch analysis. In VX.2.3, the capabilities of the Generic Batch Wizard and the Advanced Batch Wizard have been combined. Among other features, you can assign models and specify constraints at the net class level, among other features. Webinar (24 mins)

HyperLynx VX.2.3 contains many more improvements, documented in the release highlights.

For more information on the new SERDES functionality, read our white paper, ‘Is There a More Efficient Solution for SERDES Channel Analysis (or Design)?

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