SemiEngineering: Reducing Power At RTL

Excerpt from article: “Reducing Power At RTL

Other issues

Integration is also a consideration. “Accuracy of the power efficiency analysis is critical to both techniques,” said Knoth. “You cannot afford miscorrelation between what the RTL power estimation tool believes the synthesis tool will do, what the place-and-route tool will build for a clock tree, or what the signoff power tool will calculate. If you have four different tools from four different EDA vendors, when the tools don’t correlate, who’s responsible? For guided RTL reduction, miscorrelation will cause critical path slips. You’re wasting time from the most schedule-critical resources to chase phantoms. For automatic reductions, you need to have the power efficiency analysis and optimization engine embedded inside of the synthesis and implementation flow. It’s important to consider not just the power reduction, but also the timing/area/congestion impact of the changes. An example is combinatorial clock gating with XOR gates. It is relatively easy to show how it could reduce clock power. It is much harder to make sure it doesn’t introduce new implementation issues with area/congestion/timing. Only a tightly integrated solution will be safe when considering these tradeoffs.”

Practically, many times the choice comes down to the time available, observed Mohammed Fahad, product engineer at Siemens EDA. “Given you have enough time to closely look at all the suggestions, and very meticulously implement the changes suggested by the tool, you would go with the guided approach. But if you don’t have enough time at hand, and the time-to-market window is closing soon, then you would go with the automatic reduction. There are definitely many pros and cons of both. For example, in the manual flow, if you would like to retain the control of your RTL, but there is overhead for the designer doing extra change in the RTL — which wasn’t a part of their mandate, but the tool is suggesting something — then they will have to do it. The rest of the downstream flow of verification is additional. In the case of automatic optimization, if it gives a quick reduction of power at the same time, as in, ‘It’s a tool-generated RTL, you have concern of controllability of the RTL, credibility of the RTL and then the verification.’”

Read the entire article on SemiEngineering originally published on February 13th, 2020.

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