Accelerating your simulation runs. Bridging the simulation and emulation gap using Veloce sim-accel methodology
Welcome to the world of Siemens Hardware Assisted Verification (HAV) engines, a fast-paced verification ecosystem that synthesizes the design, and a large part of the testbench and then maps it to the Veloce Hardware. This setup runs 1,000 to 10,000 times faster than a simulator. So Roughly, the same design that took days and weeks now runs in minutes. That’s incredible, isn’t it?
A verification environment typically has a design under test (DUT) surrounded by verification-driven constructs. No synthesis tool can synthesize every supported keyword. Design engineers are always careful with limiting themselves to using synthesis-friendly constructs. Verification engineers are more fluid because they do not worry about synthesis. Emulators are no exception. They can synthesize the design, but the testbench runs on a host machine. The two communicate through interfaces or established standard protocols.
Now, such a system is like a relay race. The slowest player can significantly impact the overall performance. The obvious solution is to assign the shortest lap to the slowest player. Simulators are painfully slow in the relay race of emulators and simulators. How do we further reduce the time spent on simulators?
The Siemens Veloce team took a multi-pronged approach to provide a solution.
First, Veloce provides a rich set of Veloce transactor libraries (VTLs) of standard protocols and soft memory models. These VTLs are emulation-ready, geared towards performance, and support plug-and-play. A user simply replaces the simulation verification IP (VIP) with an equivalent Siemens VTL to migrate a large portion of the design. VTLs cater to large industry segments such as networking, automotive, storage, video, mobile/smartphone, and 5G, to name a few.
Siemens HAV developed eXtended RTL (XRTL), a synthesizable RTL superset. Veloce can synthesize any design or verification environment written with the XRTL-provided feature set. It includes a vast subset of verification-driven constructs such as system tasks, initial blocks, fork and join statements, memory read/write, file access, and more. One can drive a test environment written with XRTL entirely from Veloce hardware.
Third, unlike a relay race, where only one player runs at a time, components can run concurrently in a verification environment if they are not waiting for each other to provide data. Veloce leveraged this aspect to develop techniques that allow concurrent execution of simulation and emulation engine. While writing a test, the system is designed to support concurrent execution to achieve even better throughput.
Leading design companies developing large SoCs benefit from the well-adopted Veloce simulation acceleration methodology. Many articles, white papers, and customer testimonials echoing the above message are available on request. Contact us at 1-800-547-3000 for details.
The Siemens HAV group is the industry leader in simulation acceleration with its Veloce portfolio. Siemens continues to invest in supporting newer protocols, common verification IPs across simulation and emulation, and providing faster and higher-capacity hardware to meet future needs.
Saurabh Jain is a Technical Product Manager for Siemens Digital Industries Software. During his 19 years tenure in the EDA domain, he has worked in different roles as a Software developer for hardware debug technology, waveform read and write, and power analysis tools for signoff. He holds a Bachelor’s degree in Electronic and Communication Engineering and a Master’s degree in Business Administration.
