- Gearing Up For 5G
- Delving into Deep Learning
- Interrupts in the Nucleus SE RTOS
- A hardware-centric approach to checking HLS code before synthesis
- Accelerating Post-Silicon Debug and Test
Gearing Up For 5G
5G is expected to jumpstart exciting new capabilities in several markets including automotive, mobile, and the IoT. The new wireless standard will provide orders of magnitude improvements in communication speed and latency, leaving systems companies to decide whether to process their data locally or in the cloud. The choice these companies make will, to a certain degree, determine semiconductor architecture decisions going forward, from processor and memory to power budgets and more.
Delving into Deep Learning
What is deep learning? According to Chris Rowen, CEO of BabbleLabs, it is “the construction of a complex numerical model that mimics the behavior of an even more complex but hidden system. The hidden system in question is often the brain.” But, Rowen contends that an understanding of how deep learning differs from AI and machine learning is important to fully understand deep learning and its implications at the application level. Rowen spoke on this topic at a recent summit hosted by Mentor’s Emulation Division.
Interrupts in the Nucleus SE RTOS
Interrupts in microprocessors and microcontrollers provide the responsiveness necessary for many applications. However, this can conflict with the functioning of a real-time operating system that also aims to be responsive and predictable. Colin Walls explains how Nucleus SE handles interrupts to address this conflict.
A hardware-centric approach to checking HLS code before synthesis
Tech Design Forum
Traditionally, finding issues in C++ or SystemC code before passing it to high level synthesis (HLS) was tricky, potentially slowing the adoption of HLS. The crux of the problem is that static software analysis tools were not designed to understand hardware intent. Now, a new hardware-centric combination of static and formal verification techniques resolves the main limitations of previous approaches.
SoC designers are using more embedded IP, creating a challenge for post-silicon bring up and slowing time-to-market. This is partially due to the inherent inefficiencies of current silicon bring-up and debug flows that involve multiple transitions of test collateral. This article examines a new flow that enables DFT engineers to observe IP directly in the SoC under test.