Don’t Miss Mentor Graphics at DVCon US 2017!

Mentor Graphics will have experts featured in tutorials, technical sessions, booth #1101, panels, and more at DVCon 2017 February 27th – March 2nd in San Jose, CA. Don’t miss these exciting Mentor Graphics events!



2.1: DPI Redux. Functionality. Speed. Optimization
Tuesday February 28th | 9:00-10:30am


3.1: Random Directed Low-Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure
Tuesday February 28th | 9:00-10:30am


12.2: Ironic But Effective: How Formal Analysis Can Perfect Your Simulation Constraints
Wednesday March 1st | 3:00-4:30pm


13.2: Making Legacy Portable with the Portable Stimulus Specification
Wednesday March 1st | 3:00-4:30pm


Enterprise Verification Platform Required
Thursday March 2nd | 12:15-1:45pm


To stay competitive in today’s electronics industry, it is critical that design projects periodically assess emerging functional verification trends. The knowledge gained through trend analysis will help you identify new opportunities with emerging solutions, mitigate risk, and spur innovation in your own processes. This session will discuss the very latest in trends and provide you with valuable technology insights to address the requirements for a complete Enterprise Verification Platform.


Trends in Functional Verification: A 2016 Industry Study
Tuesday February 28th | 10:30-11:00am


Harry Foster, Chief Scientist for Mentor Graphics’ Design Verification Technology Division, presents the findings from the 2016 Wilson Research Functional Verification Study.

In 2002 and 2004, Collett International Research, Inc. conducted its well-known ASIC/IC functional verification studies, which provided invaluable insight into design and verification trends at that point in time. However, after the 2004 study, no additional Collett studies were conducted. Three private functional verification studies were commissioned in 2007, 2010, and 2012. Although the data from these studies has been referenced in various publications and blogs, these studies were never officially published. To address this dearth of knowledge, two new studies were commissioned in 2014 and 2016. The 2014 study was a world-wide, double-blind, functional verification study covering all electronic industry market segments. The findings from this study were published in the proceedings of the 2015 Design Automation Conference.  The 2016 study followed the format of the 2014 study and is the focus of this invited talk. The findings from the 2016 functional verification study provide invaluable insight into the state of today’s electronics industry.


Creating Portable Stimulus Models with the Upcoming Accellera Standard
Monday February 27th | 9:00am-12:00pm

Attendees will learn how to:

  • Understand and develop abstract, portable test and stimulus models for their chip designs
  • Use PSS constraints to guide randomization of both data and control flow to describe a legal scenario space to be verified
  • Target use of existing low-level sequences or drivers in the generation of tests
  • Execute generated tests across platforms from simulation, emulation, FPGA prototype, and post-silicon to verify a complete chip or multi-chip system
  • Specify and gather coverage metrics at every step to assess verification completeness


SystemC Design and Verification – Solidifying the Abstraction Above RTL
Monday February 27th | 2:00-5:00pm

Each year the EDA community makes critical advances in SystemC. As we do, the momentum toward SystemC as the primary point of entry above RTL becomes more tantalizing. Will this be the year your team makes the leap?  This tutorial could answer that question for you.

We will focus on three key components that could help you make that decision: design, modeling, and testbench. We’ll start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation will follow to complete our view of the overall design. Of course, we need to verify this fast-running design with a testbench approach that can be reused at RTL so we’ll discuss how to apply the emerging UVM-SystemC standard. We’ll complete the tutorial with a Q/A session with all of our presenters focusing on the remaining work they see to help you make the leap to the SystemC abstraction.


Stuck on a Desert Island without Simulation – Only Formal! How Do I Verify My Rescue Drone’s RTL?
Thursday March 2nd | 8:30am-12:00pm

In this tutorial you will learn how to:

  • Map your verification requirements to a human and machine readable verification plan
  • Select & run automated formal apps to expedite your verification effort without writing any SVA code
  • Setup a formal testbench and related verification methodology efficient property checking and analysis. This includes how to translate your requirements into SVA assertions, constraints, and “covers” that will be optimized for formal analysis. Not all formal runs get a complete proof on the first pass, so we will also share methodologies for dealing with “inconclusives” and how to leverage “bounded proofs” to meet your verification objectives even if a formal proof isn’t obtained.
  • Use formal-based CDC analysis to make sure none of the inter-clock domain signals go metastable
  • Use formal to check your drone’s sensitivity to logic faults so it will endure its trip to civilization
  • Close the verification loop by electronically mapping all your progress back to your original plan


Testbench Automation: How to Create a Complex Testbench in a Couple of Hours
Thursday March 2nd | 2:00-5:30pm

This tutorial is intended for verification engineers, architects and managers who are interested in making significant improvements to the overall efficiency of their verification process.

You will learn:

  • How to use the UVM-Framework code generation to rapidly build reusable testbench infrastructure
  • How to use a VIP Configurator to shorten the bring up time for industry standard protocols
  • How Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus
  • You will also hear from industry experts who have successfully used this testbench automation flow on their projects.


SystemVerilog Jinxed Half My Career: where do we go from here?
Wednesday March 1st | 1:30-2:30pm

Dave Rich – Mentor Graphics Corp.
Cliff Cummings – Sunburst Design, Inc.
Phil Moorby – Montana Systems, Inc
Arturo Salz – Synopsys, Inc.
Adam Sherer – Cadence Design Systems, Inc.

SystemVerilog will be pretty close to 15 years old at the time of DVCon-2017 (the first rumblings on the email reflectors date from spring 2002). There are plenty of working verification engineers who have used little else. This panel session calls SystemVerilog’s hegemony into question from several viewpoints. Has it provided our industry with the best we could have wished for? Has the huge R&D investment by tool vendors been justified? What kind of language or environment can we look forward to as SystemVerilog’s ultimate replacement, and how much appetite does the industry have for any such change? A panel of expert users, implementers and other stakeholders will bring their combined experience to this discussion. Expect strongly held views, radical alternative suggestions, and insights into how the needs of our industry will be served – and maybe not served – by our choice of programming languages.


Tuesday February 28th | 10:30am-12:00pm

4P.7 Systematic Speedup Techniques for Functional CDC Verification Closure

4P.13 Free Yourself from the Tyranny of Power State Table with Incrementally Refinable UPF

4P.14 Increased Regression Efficiency with Jenkins Continuous Integration Before You Finish Your Morning Coffee


Visit Mentor Graphics at booth #1101 and view the latest Enterprise Verification Platform demos including: Low Power, Formal, Verification IP, Debug, Acceleration and more!

Monday February 27th | 5:00-7:00pm
Tuesday February 28th | 2:30-6:00pm
Wednesday March 1st | 2:30-6:00pm

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