Mentor Graphics at DesignCon 2017

Join Mentor Graphics at DesignCon 2017 in Santa Clara, CA January 31 – February 2. DesignCon is the premier conference for chip, board, and systems design engineers. This year Mentor experts will be giving booth demonstrations, technical sessions, and workshops.

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TECHNICAL SESSIONS
Optimization Methods for High Speed SERDES Channels Using COM Metric
Wednesday, February 1 | 11:00-11:45am

Cristian Filip – Product Marketing Manager High Speed Analysis Products SDD, Mentor Graphics Corp.
Daniel DeAraujo – Principal Engineer, Mentor Graphics Corp.
Michael Rowlands – Principal Electrical Engineer, Molex
Priya Guruswamy – Vemparala Guruswamy, Priya, University of Colorado, Boulder

 

Demand for higher bandwidth has greatly increased the signaling data rates for SerDes. Cost effective implementation of these high bandwidth channels across high volume manufactured products require analysis of many design and manufacturing parameters. Some of the challenges in these designs is to:

1) Critical parameter identification
2) Design Space Exploration
3) Design Optimization

This paper explores the application of Channel Operating Margin (COM) as criteria for validation and optimization as well as the pros and cons of several analysis and optimization methods such as DOE, RSM, and evolutionary computation techniques.

Takeaway: The audience will learn how various optimization methods can be used during the design process, in order to properly assess the impact of various parameters on the channel’s performance, while taking into account manufacturing tolerances.

 

Channel Operating Margin (COM) for PAM4 Links with Support for TX Non-Linearity and Time Skew
Thursday, February 2 | 11:00-11:45am

Vladimir Dmitriev Zdorov – Principal Engineer, Mentor Graphics
Maria Agoston – Principal Engineer, Tektronix
Pavel Zivny – Domain Expert, Tektronix

 

COM – Channel Operating Margin, – is a copper link margin and pass/fail tool popular in PAM-2 and PAM-4 25 Gb/s and faster standards. COM relies on a number of simplifications, e.g. the linearity of the link and the validity of superposition of channel’s edge or symbol response; the non-linearity of the link is considered to be part of the penalty. However some of the transmitter non-linearity can be an advantage, rather than a penalty.  We consider a number of modifications to COM which make it applicable to non-linear PAM-4 links.

Takeaway: COM (Channel Operating Margin), a link margin tool considers non-linearities mostly as uncompensable penalty. However applications of PAM-4 can benefit from certain non-linearities. We show the advantage of handling non-linearities in the link. We propose a refinement of COM with fair treatment of non-linearity of Tx in PAM-4 links.

Prerequisites: General understanding of PAM-2 and PAM-4 modulation, transmitter non-linearity, equalization, ISI, jitter, statistical analysis, COM

 

SI Analysis of DDR Bus During Read/Write Operation Transitions
Thursday, February 2 | 4:00-4:45pm

Nitin Bhagwath – Technical Marketing Engineer, Mentor Graphics
Arpad Muranyi – Staff Engineer, Mentor Graphics
Randy Wolff – Principal Engineer, Micron
Atsushi Sato – Senior Manager of Custom SoC Development Division, Socionext Inc
Shinichiro Ikeda – Manager of Custom SoC Development Division, Socionext Inc.

 

Traditionally, the Read and Write transactions of (LP)DDRx DQ busses have been analyzed independently. Transitions from one operation to another have usually been prioritized lower.

At lower speeds, this prioritization might be justified, but at the higher speeds of (LP)DDR4, this comes into question. The SI effects between operations make it very important to simulate at higher speeds.  Such analysis will require methodologies and modeling approaches beyond what has traditionally been practiced. Find out under what conditions your (LP)DDR bus’s SI will be impacted by operation transition, and how to perform simulations required to achieve a robust design.

Takeaway: (LP)DDRx busses, with ever shortening time periods between the operations, simulating transitions from one operation to another (read-to-write, write-to-read, or accesses to different ranks) are becoming a greater challenge and more critical. The paper will inform the reader when and how to perform simulations to model operation transitions.

 

BEST PAPER AWARDS
Vladimir Dmitriev-Zdorov will receive the Best Paper Award in the T&M Category for his 2016 DesignCon Paper “BER- and COM-Way Channel Compliance Evaluation: What are the Sources of Difference?”. You can download a copy of the paper here.

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DesignCon Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation at DesignCon.

 

EXHIBIT FLOOR
Stop by booth #1043 to speak with our experts, or schedule an appointment at PCB_Events@mentor.com.

 

The Mentor Graphics booth will be showcasing:

  • HyperLynx Signal Integrity
  • HyperLynx Power Integrity
  • HyperLynx DRC
  • HyperLynx Full-Wave Solver
  • Frontline InStack Design

 

We look forward to seeing you there!

 

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/expertinsights/2017/01/25/mentor-graphics-at-designcon-2017/