A hypervisor on a multicore system
I have written before about multicore systems – here for example – and looked at AMP vs SMP and various other aspects of the technology. As the use of multicore designs has become increasingly mainstream, the options and possible configurations available has increased drastically.
A particular facet is the incorporation of a hypervisor in an AMP system …
All embedded systems have finite resources, which need to be managed. It may be argued that this is the crux of what embedded software development is all about. For the purposes of this discussion, I want to consider a hypothetical example system which has a single serial port. There are various ways that this port may be managed, depending on the configuration of software and CPU hardware.
On a single core system, the operating system can manage access to the serial port and arbitrate between multiple tasks that might wish to make use of it. There are lots of ways that this might be achieved and this is a well trodden path.
If the system has multiple, identical cores, it might be useful to configure it as SMP – a single operating system instance running across all the cores. SMP versions of many RTOS products [like Nucleus] are available and Linux with SMP support is also an option. This approach is ideal if the application benefits from the OS being able to distribute CPU power as needed. The OS can manage access to the serial port in much the same way as on a single core system.
On many systems SMP is unattractive, because more precise control is required or the system has so many cores that performance degradation is likely. On others, SMP is impossible, because the cores are not identical. In these cases, an AMP configuration, with a separate OS instance on each core, makes sense. This presents a challenge: how might the single serial port be managed?
If all the cores in the system are suitable for running a hypervisor [ARM A15 for example], a possibility is to run it on all of them, with each core’s OS considered to be a “guest”. Access to the serial port may then be managed by the hypervisor.
If one or more of the cores are not capable of running a hypervisor [like an ARM M4 for example], an alternative option is available in the form of the Heterogeneous Multicore Framework [HMF] from Mentor Embedded. This facilitates management of the smaller core by the hypervisor running elsewhere [on something like an A15 on the same chip]. Thus, the hypervisor can manage access to the serial port by all the cores in the system, whether they are running the hypervisor or HMF.
This short video expands on some of these concepts and shows a real application that uses a hypervisor in an AMP system:
This is, I am sure, a topic to which I will return.
