More on low power CPU design

I recently wrote a posting about designing a CPU for low power by creating an instruction set where common sequences of instructions would have the minimum number of logic transitions. I hoped that I would get some feedback and I did. I had an email from Apostolos Leventis. I am always delighted to be contacted by blog readers, either by comment or email – even if it is critical or correcting my errors!

In this case, I was fully prepared to hear that the approach that I described would not work for some reason. However, what Apostolos told me about was some work that approached the problem in a different, but very interesting way …

The approach that I talked about would involved designing a new CPU. The project, that Apostolos had been involved in, looked at the optimal use of existing devices and the generation of power-efficient code for them.

The work was done using an ARM7tdmi and a DSP56156. The team did measurements on the devices to identify instruction sequences which were particularly power efficient. They then created a compiler which could generate power-optimized code by utilizing these findings. They tested the tools on an implementation of IEEE802.11 and observed power savings of up to 10% [for just the CPU].

The full paper may be found here. I thought that this research was very interesting and I am sure could be carried further. I would like to thank Apostolos for sharing.

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