What’s New in Xpedition VX.2.4 – Design Verification

By John McMillan

In the previous What’s New in Xpedition VX.2.4  blog post, I reviewed the new Layout functionality that is available in Xpedition VX.2.4.  In this blog post, we’ll take a look at what’s new in the area of Design Verification.

Xpedition design verification functionality includes a complete suite of high-speed PCB simulation tools powered by HyperLynx®. Capabilities include signal integrity, power integrity, analog/mixed-signal, full wave, thermal, and vibration analysis. This functionality also includes powerful DRCs for EMI/EMC, SI, and PI design verification.

Lets take look at some of the VX.2.4 Design Verification highlights!

DC Drop – Rigid-Flex & Multi-Board: The VX.2.4 release brings additional support for rigid-flex and multi-board analysis. Power integrity enhancements include seamless DC drop simulation and analysis for rigid-flex designs. Unique stack-up by areas and their individual characteristics are seamlessly transferred from layout.

Constraint Integration: New to HyperLynx BoardSim is constraint integration, enabling users to create a wide range of signal integrity constraints and net class assignments. For comprehensive batch SI analysis, users can also import constraints directly from Xpedition schematic or layout.

SERDES: HyperLynx VX.2.4 adds many usability improvements for SerDes. FastEye capability is now included within the SerDes batch wizard and requires no IC models. New operating modes in the channel-compliance analyzer, for PCIe Gen 1 (2.5 Gbps), Gen 2 (5Gbps), and Gen 5 (32Gbps), 50GBASE-CR, and JESD204C–JCOM, bring the number of supported channels to 34.

Schematic Verification Integration: Schematic Integrity Analysis can now be launched, and new projects created, directly from within the schematic design menu. Quickly analyze a design’s Bill of Materials, netlist, and voltages. Full forward- and backward-annotation are supported, as are design check-out and check-in.

Electrical Rules: HyperLynx VX.2.4 brings many new electrical design rules, including analog rules for net under component, component isolation, and sensor net isolation. New power integrity rules include PDN isolation and grounding layer. Creepage rules were added and enhanced to perform distance calculations on any layer of the PCB. To save research time, additional IEC international standards and charts were also integrated into the tool.

Valor NPI Integration: A new Valor NPI add-in enables iterative, concurrent design analysis for quick and easy review of DFF results within the Xpedition hazards explorer. It supports fabrication, flex, HDI, and microvia analysis. Marked issues don’t appear in subsequent analysis, enabling you to correct or ignore hazards as desired.

DFM = MRA: Enhanced ease-of-use in Valor NPI with MRA (Manufacturing Risk Assessment) enables layout designers to run rules during layout rather than having to rely exclusively on work done by an NPI specialist post-layout. To ensure that only real issues and hazards are reported, users can set up and maintain their own DFM rules.

If you would like see a video demo of these Layout enhancements as well as all of the other new features and enhancements in this release, please check out the What’s New in Xpedition video, along with online demos of the highlights for each of the VX.2 releases. You can also take a quick tour of Xpedition Enterprise to get a great overview of all the functionality that Xpedition has to offer.

Be sure to check back shortly for the next entry in this series – What’s New in Xpedition – FPGA-PCB Co-Design .

Leave a Reply

This article first appeared on the Siemens Digital Industries Software blog at