3D-IC design using Calibre 3DSTACK

By Minjung Han (minjung.han@siemens.com), Calibre Support Application Engineer

3D-IC technology is gaining attention as an alternative to complement Moore’s Law, which is approaching its physical limits. Unlike traditional 2D IC design, 3D-IC requires a differentiated verification process. In particular, Electronic Design Automation (EDA) solutions have become essential tools to support this transition.

Calibre 3DSTACK offers a comprehensive solution for verifying heterogeneous designs. This video provides a detailed explanation of how Calibre 3DSTACK performs verification in 2.5D and 3D-IC designs and the benefits it brings.

Challenges

Efforts to overcome the limitations of 2D semiconductor design continue, but there are still challenges related to technology and cost. Issues that may arise during the stacking and placement of various dies are often difficult to predict. Even if DRC, LVS, and PEX verification has been completed for a 2D design, there is no guarantee that a 2.5D or 3D-IC will function correctly after assembly. Therefore, while different design processes progress independently, a comprehensive verification step is required once again to ensure reliability.

Solution

Calibre 3DSTACK provides a fast and accurate solution for verifying potential issues in 2.5D and 3D-IC designs. By using Calibre 3DSTACK, designers can identify and resolve potential errors early in the process, before the design is physically assembled.

For more details on how to use Calibre 3DSTACK, check out the Calibre 3DSTACK video series available at the link below.

Calibre 3DStack video series part 1

Calibre 3DStack video series part 2

Calibre 3DSTACK video series part 3

Calibre 3DSTACK video series part 4

Calibre 3DSTACK video series part 5

By Minjung Han (minjung.han@siemens.com), Calibre Support Application Engineer