Google team accelerates high-sigma bitcell validation with Solido Design Environment
Google’s Akash Jha shares how his team deploys Solido AI-powered technologies at the Custom IC Forum in Bangalore.
This September, the Solido team traveled to India for the annual Solido Custom IC (CIC) Forum in Bangalore where we were joined by over 400 members of the design community from across the region.
This year’s forum centered on a powerful theme: AI-powered variation-aware verification, simulation, IP validation, and design technologies, with a strong focus on real-world applications and customer success stories.
Representatives from 8 of the top 20 semiconductor companies joined us on stage to share how they use Solido technologies to accelerate and advance their workflows, including Akash Jha and Naveen Kumar M from Google who presented their innovative approach to bitcell verification with Solido Design Environment tools.
High-sigma verification: a challenging but necessary step
The Google team leveraged the AI-powered technologies in Solido PVTMC Verifier and Solido High-Sigma Verifier to qualify their bitcell design to a >6-sigma reliability standard for all read, write and hold operations. Trying to accurately verify this design using traditional methods would have been infeasible, given the enormous number of brute-force simulations needed to validate high-sigma circuits. Without high-sigma analysis, the risk of an expensive silicon failure is high due to significant variations from the fabrication process and a highly-replicated circuit.
Google team’s Solido-based methodology for accelerating high-sigma bitcell verification
To start their workflow, the Google team used Solido PVTMC Verifier to identify the absolute worst-case PVT corners for each operation. Then, they ran Solido High-Sigma Verifier to execute a focused statistical analysis on that worst-case corner. Finally, the Google team ran a specialized flow called High-Sigma Parameter Solver (HSPS), which solves circuit inputs for a specific output target. Using HSPS, they verified an ultra-low <500mV Vmin to determine the bitcell’s true Vmin while ensuring 6-sigma reliability.
Solido AI-powered verification technologies propel Google team to successful test chip validation
As a result of their Solido-based workflow, the Google team established a variation-aware timing guardband for the final library by directly incorporating the results of their Solido-based 6-sigma analysis. The final design was taped out for silicon validation in a test chip, marking the successful completion of the pre-silicon phase.
Ready to achieve 6-sigma reliability in your next design?
Discover how Solido Design Environment can transform your verification workflow. Learn more about the technologies that enabled Google’s success at eda.sw.siemens.com/en-US/ic/solido/design-environment/.
