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The next steps in 5G: logic design and verification challenges

The massive buildout for 5G communications is just getting underway. While the promises of its technological and economic impact are yet to be fully realized, the expectation is that the innovation will exceed $13 trillion while adding over 22 million jobs.

To keep pace with these expectations, companies face challenges in delivering 5G-ready platforms that allow them to compete with a massive marketplace.

Meeting the 5G logic and verification challenges with Siemens EDA solutions via the Siemens Xcelerator portfolio can provide higher levels of success and 5G adoption.

Early decision-making in 5G communication platforms

Engineers are constantly managing increasing numbers of electronic components in everything from a handset to mobile phones to the infrastructure equipment that will help successfully implement our 5G world.

A smart phone, for example, begins with high-level engineers tasked with the architecture design before its creation. Decisions at this level are centered around system functionality and the requirements of the 5G phone, this even includes the power plug and cameras as well as its capabilities to communicate in 5G and backward compatibility to 4G, all of which will impact battery life.

Given all those specifications and constraints, the engineers must figure out what they need the chip and all of the electronics to do to run all of the operations. What can they consolidate and what system functionality can they integrate into one chip?

There are several tools available in the Siemens Xcelerator portfolio that electronics engineers and other decisionmakers are using to create the 5G communications technology.

In the white paper: How Siemens EDA helps you engineer smarter 5G communications systems faster, there are several 5G IC logic design and considerations and the solutions available to fulfill the grand vision of 5G. Here are some of the considerations you’ll read about:

Logic design. Solutions for IC design, verification, and validation of digital front end, fronthaul 5G ICs and other digital blocks. It helps designers develop a correct-by-construction register transfer level (RTL) code representation of their design.

Logic verification and validation. The RTL code can then run through verification and simulation solutions to find and then resolve issues that allow for full-chip functional verification of the RTL code and validation of the IC design.

Mixed-signal verification. Accurately verify the links between the analog, high-frequency RF and digital domains. This is essential for SoC designs in 5G mobile/edge devices and 5G fronthaul equipment.

Library characterization. Implementation/design tools can characterize a given IC design’s building blocks and are robust enough for 5G applications. Siemens EDA offers machine learning to derive accurate results faster. Engineers can also use an advanced library validation, analysis, and debugging solution that includes fast, parallelized, and comprehensive static rule-based checks, and employs a machine learning outlier detection tool that “learns” the expected characterized values in a library and automatically detects errors that typically go undetected with other tools.

Ready to learn more about how Siemens EDA is playing a role in helping companies design and verify their 5G products?

Download How Siemens EDA helps you engineer smarter 5G communications systems faster.

Discover how Siemens Xcelerator helps companies turn complexity into a competitive advantage.

Steven Hartman

Steve Hartman is a Thought Leadership writer for Siemens PLM Software. Steve’s experience is varied spanning the automotive, financial, real estate, travel and sporting goods industries as well as having written four published novels and co-wrote a memoir. He has a wife, three kids, two dogs, a cat and a rabbit. And still, he carves out time to read, watch movies and write.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/xcelerator/2022/06/13/5g-logic-design-and-verification-challenges/