It’s obviously a good thing to include X-propagation analysis in your constrained-random simulation testbench flow.

Reducing Area and Power Consumption while Increasing Performance with Formal-based ‘X’ Verification

[Preface: on October 15 at 8am Pacific, Product Engineer Ping Yeung will be delivering a free, detailed technical webinar on…

Easy Deadlock Verification and Debug with Advanced Formal

DAC 2020 Paper Report: Easy Deadlock Verification and Debug with Advanced Formal Verification

At this year’s Design Automation Conference (DAC), Formal verification was everywhere – in posters, papers, and panel discussions – where…

The Many Flavors of Equivalence Checking: Part 5, Summary of the Most Popular LEC and SLEC Use Cases

As I noted at the beginning of this series, the term “logic equivalence checking” (LEC) applies to a number of…

The Many Flavors of Equivalence Checking: Part 4, How SLEC Brings Automated, Exhaustive Formal Analysis to Safety Mechanism Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, Part 2 describes how…

The Many Flavors of Equivalence Checking: Part 3, How SLEC Brings Automated, Exhaustive Formal Analysis to Low Power Clock Gating Verification

[Preface / reminders: Part 1 of this series focused on synthesis validation with LEC and SLEC, and Part 2 describes…

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

FMCAD 2019: The Most Important Formal Verification Conference You’ve Never Heard Of

[Preface: I briefly interrupt my series on The Many Flavors of Equivalence Checking to share this report on an important…

The Many Flavors of Equivalence Checking: Part 2, How SLEC Brings Automated, Exhaustive Formal Analysis to ECO/Bug Fix Verification

Perhaps the only Sequential Logic Equivalence Checking (SLEC) flow that is as common as the synthesis validation flow described in…

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

The Many Flavors of Equivalence Checking: Part 1, Synthesis Validation with LEC and SLEC (a/k/a the Most Popular Formal Apps Ever)

In EDA, the word “simulation” is used everywhere: there is RTL and gate level simulation, analog simulation, RF simulation, and…

How to Reduce the Complexity of Formal Analysis – Part 6 – Leveraging Data Independence and Non-Determinism

How to Reduce the Complexity of Formal Analysis – Part 6 – Leveraging Data Independence and Non-Determinism

If you know the dependencies – or lack thereof – in your design, you can exploit two very fundamental characteristics…