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Chris Spear

Chris brings over forty years of EDA expertise to Siemens customers. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 12,000-foot mountain passes.

UVM Configuration DB Guidelines

UVM Configuration DB Guidelines

May 7, 2020

Introduction My previous blog posts were on static and parameterized classes to get you ready for the big game –…

By Chris Spear
3 MIN READ
SystemVerilog Static Methods

SystemVerilog Static Methods

April 29, 2020

Introduction In my last post, you learned how to create a class with a static property. This variable acts like…

By Chris Spear
2 MIN READ
SystemVerilog Classes with Static Properties

SystemVerilog Classes with Static Properties

April 21, 2020

Introduction One of the advantages of creating your testbenches with Object Oriented Programming, as opposed to traditional procedural programming, is…

By Chris Spear
2 MIN READ
SystemVerilog Parameterized Classes

SystemVerilog Parameterized Classes

April 16, 2020

SystemVerilog allows you to create modules and classes that are parameterized. This makes them more flexible, and able to work…

By Chris Spear
2 MIN READ
Tips for new UVM users

Tips for new UVM users

April 1, 2020

Or: What I forgot in class When I first learned UVM, there were many things that baffled me. What was…

By Chris Spear
3 MIN READ

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