DFT architectural tips: the importance of reference flows

This video, the last in a series of three, discusses the Tessent platform capabilities and the reference flows, test cases, and documentation that help ensure DFT successes for flat, hierarchical, or hybrid ATPG/BIST flows.

DFT insertion for chips with many hierarchical physical regions can be challenging. The Tessent platform is an integrated DFT solution that covers memory BIST, logic BIST, analog/mixed-signal, MissionMode test for automotive, boundary scan, IJTAG integration and verification, compression and ATPG, and scan chain insertion.

To hear more about the broad capabilities of the Tessent DFT platform, including the reference flows, test cases, and documentation that comes with the Tessent software, watch this short video from Mentor’s Vidya Neerkundar.