Intel’s dramatic test quality improvement with Tessent

Intel used the Tessent cell-aware, defect-oriented test to reap stunning reductions in DDPM for an automotive IC. Intel Principal Engineer Will Howell tells you all about it in this video.

Defect-oriented test refers to practices that improve test generation to achieve better defect coverage for a manufactured design. You see the term more often now that more IC makers are aiming for “zero-DPPM” devices targeted to automotive applications. The application of defect-oriented test is the focus of this presentation by Will Howell, principal engineers at Intel, recorded live at the 2018 International Test Conference.

The adoption of defect-oriented test methods is driven by the use of 3D transistors, which come with increased transistor process complexity and many more systematic defects. It is estimated that a full 90% of defects are now located inside of cells. The trend of transistor complexity is expected to increase with gate-all-around transistors and transistor stacking.

Classical fault models (like stuck-at and transition) are unable to satisfy the demands for high-quality devices, says Howell. His team built a comprehensive defect enumeration strategy to identify and test likely defects and meet the quality requirements for ICs for use in autonomous systems.

Howell describes how his team dramatically improved DPPM with Mentor’s defect-oriented test methods. Intel applied the Tessent timing-aware, cell-aware test patterns to target small-delay defects of FinFET transistors.

Cell-aware test helped them figure out which defects matter, how they express themselves, and how to actually detect them on the tester. For this experiment, Intel achieved a 4.3k DPPM improvement, which Howell calls “stunning.”

Watch the 7-minute video now to hear more details about the work Intel did with cell-aware ATPG and how it helped them meet their IC quality goals.