Mentor showcases machine learning and more at VLSI Test Symposium

Mentor’s Tessent DFT and yield experts will have a strong showing at the IEEE VLSI Test Symposium (VTS) 2018, which runs from April 22 – 25 in San Francisco. VTS explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems.

Mentor experts will present the morning tutorial on the first day, moderate 5 sessions and present 6 original research papers (2 with partners).

Register for the VLSI Test Symposium (VTS) here

Here’s the line up of sessions and presentations by Mentor’s Tessent test experts:

• Morning tutorial Machine Learning and its Applications in Test, led by Yu Huang and Gaurav Veda. The exciting field of deep learning has become more useful with the availability of powerful (and free) libraries. The presenters review recent important research in which machine learning algorithms are used to improve DFT, diagnosis, yield learning, and root-cause analysis.
• Analog Test session moderated by Mentor’s analog test expert, Steve Sunter.
• Mentor and Intel scientists present Memory Test Capabilities for Addressing Test Cost Reduction and Functional Safety Needs.
• Memory session moderated by Mentor scientist Martin Keim.
• Presentation by Steve Sunter Measuring ISO 26262 Metrics and Fault Coverage Simultaneously for A/MS Circuits.
• Presentation by Mentor and two university partners Staggered ATPG with Capture-per-Cycle Observation Test Points.
• Machine Learning for Emerging Applications session moderated by Yu Huang.
• Kareem Madkour presents Overcoming the Challenges of Hotspot Detection using Deep Learning.
• Machine Learning for Test and Diagnosis session moderated by Yu Huang.
• Gaurav Veda presents Supervised Techniques for Volume Diagnosis.
• Michael Chen presents Finding Opportunities to Apply Hardware Security.
• Finally, the Test Data Analysis session moderated by Mentor’s Janusz Rajski.