What’s New in Mentor Functional Verification

Just like time and the tides, the complexity of electronic systems, and the need to verify that they will function correctly, wait for no one. This 5-part web seminar series provides a comprehensive overview of Mentor’s Functional Verification tools and shows how each has been optimized to find bugs as early in the verification process as possible. Each session will be presented twice at the times shown below consisting of two half-hour presentations, with Q&A. Please register for the time that is more convenient for you.

Sessions:

Session 1 – Keynote: Optimizing Time to Bug & Productivity in the Questa Simulation Flow

• Thursday, May 14th
• 4:00 PM – 5:00 PM Europe/London
• 4:00 PM – 5:00 PM US/Pacific

Session 2 – Market-Driven Trends in Hardware Emulation & Context-Aware Debug for Complex Heterogeneous Environments

• Thursday, May 21st
• 4:00 PM – 5:00 PM Europe/London
• 4:00 PM – 5:00 PM US/Pacific

Session 3 – Maximize Your UVM Productivity with Protocol-Aware Questa Verification IP & Find Bugs Earlier with Strategy-Guided Stimulus

• Thursday, May 28th
• 4:00 PM – 5:00 PM Europe/London
• 4:00 PM – 5:00 PM US/Pacific

Session 4 – Improving Quality and Time-to-Market with Formal: Part 1, Automated Formal-based Apps & Improving Quality and Time-to-Market with Formal: Part 2, Direct Formal Property Checking

• Thursday, June 4th
• 4:00 PM – 5:00 PM Europe/London
• 4:00 PM – 5:00 PM US/Pacific

Session 5 – Confronting Inevitability: Finding Clock and Reset Issues Before They Find You & Mentor + Siemens Provides Solutions and Expertise to Achieve Rapid Safety Compliance

• Thursday, June 11th
• 4:00 PM – 5:00 PM Europe/London
• 4:00 PM – 5:00 PM US/Pacific

Learn more and register.