Get Your Bits Together: SystemVerilog Structures and Packages
Chris Spear, Principal Instructor will present a detailed description of structures and packages in the SystemVerilog language. You can model your hardware registers down to the bit level, or build complex data types that contain a mix of different elements such as 4-state logic, 2-state integers, real numbers, and enumerated types. In addition, you will be shown how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused. We will also be discussing problems and best practices with packages. For more details, please see here.