Mentor at the 55th Design Automation Conference

Mentor at the 55th Design Automation Conference

The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. This year’s event will be held in San Francisco, California at Moscone Center West from June 24-28, 2018.

Each day is full of exciting activities featuring Mentor technical experts on the latest in cutting-edge design. You’ll find our experts in the conference program, in our booth (2621) hosting suite sessions and networking events. You can also find us at the booths for Verification Academy (1622), Tanner EDA (1337), and Solido Design Automation (1344).

CONFERENCE HIGHLIGHTS
Mentor experts will be featured throughout the technical conference program:

• 7 paper presentations
• 13 posters
• 2 panels
• 2 expert tutorials

 

Straight talk with Wally Rhines
Wally Rhines, President and CEO of Mentor, a Siemens Business, sits down with Semiconductor Engineering’s Ed Sperling to discuss the big shifts in technology, from AI to autonomous cars to the growth of the Internet of Things and the Industrial Internet of Things. What kinds of shifts can we expect to see in the future, who’s going to be best positioned to take advantage of them, and what will the semiconductor industry look like in five years as these changes begin taking hold? Who will be the winners and who will be the losers?

Special Session: A Modular Digital VLSI Flow for High-productivity SoC Design
DARPA’s new Circuit Realization At Faster Timescales (CRAFT) program has as its goals to reduce by 10X the effort required to design and verify complex SoCs in leading edge CMOS technology and to reduce by 5X the effort required to port designs to a new fabrication process. This session will describe some of the key results from the first 15 month phase of the program, including work performed by teams led by NVidia, UC-Berkeley, and UC-San Diego

EXHIBIT BOOTH (2621) HIGHLIGHTS
We’ve brought some of our best researchers and partners to DAC just to meet you. Stop by our Cappuccino Bar and Happy Hour daily and grab a free drink!

Choose from over 70 technical sessions across 7 technical focus areas:

• IC Design & Test
• Design & Functional Verification
• Analog/Mixed-Signal and Custom IC Design
• High-Level Synthesis, Low-Power, and SLEC
• Emerging Markets
• Packaging & PCB
• Verification Academy

EXPERT PANELS

Catch two expert panels in the Mentor booth for exciting conversation on the latest in cutting edge design! Show up a little early and grab a complimentary beverage at our Happy Hour to enjoy during the panel!

Funcional safety – where are we going and how do we get there?

Monday June 25^th, 4:00pm – 5:00pm

Mentor Booth #2621

With everything from cars to factories to the world around us becoming more intelligent and increasingly automated, the decision making is shifting from humans to the machines. Semiconductors are at the center of this innovation but now the way these electronics are developed must evolve as humans put their lives in the hands of these transistor-based machines. The concept of functional safety is not new but with the move to autonomous driving, functional safety has been put in the spotlight for IC development teams. From requirements to fault injection, functional safety brings many new challenges for IC development but at scales and levels of automation not seen before. Join us for this interactive panel discussion.

Moderator

Bryan Ramirez, Mentor

Panelists

Fram Akiki, Siemens PLM; Sanjay Pillay, Austemper Design; Dwight Howard, APTIV; Yves Depret, ON Semiconductor

Getting your tape-out done on time isn’t easy, but it can be easier

Tuesday June 26, 4:00pm – 5:00pm

Mentor Booth #2621

More than 50% of tape-outs don’t occur on schedule. Which 50% do you want to be in? Come listen to Calibre customers talk about the challenges that they face and the steps that they take to get their tape-outs on time.

Moderator

Joe Davis, Mentor

Partner Activities 
Mentor offers the broadest support for the electronics ecosystem/supply chain. That’s why you’ll find Mentor experts sharing in a numerous partner activities on the exhibition floor—both in our booth and at our partners’ locations.

Monday, June 25^th

11:00am: Saving Weeks off the physical design implementation cycle: Qualcomm’s experience using Calibre RealTime Digital – Qualcomm

1:00pm: RTL Power Optimization on a Tight Schedule: Powerpro in Vector-Less Mode – Cisco

2:00pm: Demonstrating Functional Safety Compliance in Automotive IC Design – Austemper Design

3:00pm: Moving Data at the Speed of Light: Silicon Photonics and TowerJazz Advanced Process using Calibre – TowerJazz

4:00pm: Portable Stimulus versus UVM: What’s the Difference? – Doulos

4:00pm: Improving IC Reliability by Automating Power Net Robustness and Net-aware Fill with Calibre® PERC™, Calibre® YieldEnhancer & Calibre® Pattern Matching- GLOBALFOUNDRIES

Tuesday, June 26^th

11:00am: Building An Integrated Verification Flow – XtremeEDA

1:00pm: STMicroelectronics’ 28FDSOI IP Qualification and 22FDX RTL2GDS Using Mentor Oasys-RTL and Nitro-SoC – STMicroelectronics

2:00pm: Power Aware Simplifies Parametric PA-SIM Regression – Cypress Semiconductor

3:00pm: TowerJazz Automotive Reliability for Analog Constraint Checks and the Calibre® PERC™ Reliability Verification Platform – TowerJazz

4:00pm: Design and Verification of a Machine Learning Accelerator SoC Using an Object-Oriented HLS-Based Design Flow – NVIDIA

4:00pm: Superbugs: Leveraging Formal Verification to Combat Simulation Resistant Bugs – Oski Technology

5:00pm Using Automation to Close the Loop Between Functional Requirements and their Verification – Cypress Semiconductor

Wednesday, June 27^th

11:00am: Virtual Method Upcasting & Downcasting And Their Use In UVM – Sunburst Design

1:00pm: 7nm SRAM physical verification solved with Calibre Pattern Matching- TSMC

3:00pm: YE Flows in P&R- Qualcomm

Make sure you’re following us on Twitter (@Mentor_Graphics) for the latest conference news, pictures, and happenings!