Article Roundup: Accelerating Industry 4.0 for Electronics Manufacturers, Mentor Adds Circuit Simulators to the Cloud using Azure, ITC shines light on new Mentor Test announcements, Taking the Guesswork out of DDR Design with integrated schematic, Layout and Simulation Tools, Speeding Up 3D Design
1. Accelerating Industry 4.0 for Electronics Manufacturers
2. Mentor Adds Circuit Simulators to the Cloud using Azure
3. ITC shines light on new Mentor Test announcements
4. Taking the Guesswork Out of DDR Design with Integrated Schematic, Layout and Simulation Tools
5. Speeding Up 3D Design
Accelerating Industry 4.0 for Electronics Manufacturers
EMSnow
A unified, holistic approach to digitalization is one of the pillars of Siemens’ recently released Opcenter Execution Electronics solution. Leveraging the multi-domain production solutions in Siemens Digital Industries Software portfolio, Siemens Opcenter Execution Electronics harmonizes collaboration across all of these manufacturing management areas. The solution incorporates in a single solution the Siemens Opcenter Execution Electronics MES technology and box-build functionalities with manufacturing solutions provided by the Valor tools. Learn more on how electronics manufacturers seek to build an Industry 4.0 operation from this article.
Mentor Adds Circuit Simulators to the Cloud using Azure
SemiWiki
EDA tools started out with mainframe computers, the early progenitor of cloud-computing, and now with vendors like Microsoft we have returned to centralized computing again because it makes sense for peak EDA tool run requirements. In this article, read more on Mentor’s recent announcement on circuit design engineers, who can now simulate their SPICE netlists in the Azure cloud, scaling to 10,000 cores.
ITC shines light on new Mentor Test announcements
SemiWiki
This article throws light on Mentor’s new announcements during the 50th International Test Conference (ITC). The first announcement covers Mentor’s Tessent Connect methodology that supports hierarchical DFT & helps IC design teams achieve IC manufacturing test quality goals more quickly. The second announcement describes the Tessent Safety ecosystem that helps IC design teams meet increasingly stringent functional safety requirements of the global automotive industry. If test methods had grown linearly with design size and complexity, today’s massive designs would be effectively untestable. At the same time test activity has moved from being a manufacturing step into something necessary throughout the life of the design in many applications.
Taking the Guesswork Out of DDR Design with Integrated Schematic, Layout and Simulation Tools
EEWeb
The powerful features available in HyperLynx DDR allow engineers to visualize real-world performance impediments at all stages of the design process. With this technology, it is possible to catch and reverse, as well as completely avoid critical signal integrity complications before they ever happen. With integrated simulation and design tools, users can take the guesswork out of the DDR design process while eliminating complicated signal integrity issues and preventing expensive board re-spins. Read this article to know why DDR memory is quickly becoming not only the leading technology but the only technology used in memory design.
Speeding Up 3D Design
SemiEngineering
The tools and techniques available today enable basic approaches to 3D stacking, but they are not yet at a point where all of the potential can be unleashed. Some of the issues are understood, but the solutions to them today involve playing it safe and attempting to avoid the problem. Read this article to find out why the chip industry is plowing ahead with advanced packaging and what can be done to improve it.
