Automotive Innovation at DAC
Automotive system design is fully-charged at the 55th Design Automation Conference. The automotive conference sessions provide a forum for engineers from automotive, embedded systems, security and EDA, to connect, engage, and exchange information.
You’ll also find the latest in cutting edge automotive design each day in the Mentor booth (2621) and Verification Academy booth (1622) from June 19-21. Our experts will cover a wide array of automotive system design topics including ISO 26262, IC design, verification, security, and test. Mentor’s advanced systems engineering expertise, tools, and platforms enable teams to add innovative technology to vehicle designs earlier and with more confidence.
Take a look at our planned sessions below and register for your favorites. Seats fill fast, so reserve your spot today!
FEATURED PANEL
The Automotive Digital Twin, Virtual or Virtually Impossible
It’s estimated that 14.2 billion miles of road testing will be required as cars reach levels 4 and 5 autonomy. Hence, some engineers argue that this is impractical and that traditional ways of testing simpler electronics using physical road testing simply will not scale. Enter the Digital Twin. The Digital Twin sets out to virtually model the complete development of these complex systems such that they can be architected, designed and tested 100% digitally before any physical hardware is created. The promise is that this will shift-left development cycles, increase quality and reduce development costs. But can a Digital Twin accurately and effectively represent an entire autonomous car to eliminate the old ways of physical validation—particularly with emerging safety requirements (ISO26262), as well as the emergence of artificial intelligence as controls? This panel of experienced technical experts will debate the pros and cons of realizing the automotive Digital Twin in Room 3020
Presenter: Bill Taylor, kVA
Presenter: Dwight Howard, Aptiv
Presenter: Kurt Shuler, Arteris, Inc
Presenter: Sanjay Pillay, Austemper Design
TECHNICAL SESSIONS IN BOOTH 2621
TowerJazz Automotive Reliability for Analog Constraint Checks and the Calibre® PERC™ Reliability Verification Platform
With the continued transition for more advanced electronics solutions in the automotive arena, the need for ensuring highly reliable semiconductors has become imperative. Calibre® PERC™ automotive reliability check templates were developed as an outcome of the German RESCAR 2.0 program, which is focused on increasing robustness of electronic circuits in automotive environments. Member companies Infineon Technologies AG and Robert Bosch GmbH of this program selected the Calibre PERC platform as the electronic design automation (EDA) reliability platform, with the Calibre PERC-based automotive reliability check templates for the verification of essential robustness constraints. TowerJazz is the first commercial foundry to incorporate these RESCAR-developed reliability checks into their standard Calibre PERC design kit offering. These checks enable designers to address the enhanced level of reliability compliance that automotive industry standards, such as the international functional safety standard ISO 26262, are now requiring from the entire automotive supply chain. Join us to learn how these checks, while focused on analog design, can be used to analyze and enhance the reliability of any IC.
Automotive IC reliability solutions with Calibre®
The automotive industry continues to push for greater IC performance and reliability. In the area of functional safety, compliance to standards like ISO 26262 are of great importance. All areas of the automotive IC ecosystem provide challenges for those accustom to consumer electronic standards looking to enter this expanding market. Join us for an overview of how the Calibre® products support customer ISO 26262 certification efforts and aide with improving overall IC reliability and productivity.
Verification of Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles with Hardware Emulation-In-The-Loop
OEMs are taking control of ECU hardware/software architecture definition and exploration due to rise of new technologies in ADAS and autonomous vehicles. The need to accelerate the simulation of thousands of driving scenarios and design parameters to ensure safety in autonomous driving has expanded the use of hardware emulation in the loop based on its capacity and functional verification merits. In this session, an integrated heterogeneous system of systems framework to simulate and verify multiple ECUs is presented. It allows co-development of AUTOSAR software and ECU hardware together with mechanical system actuators, sensors, and traffic scenarios all in one.
Automotive Semiconductor Reshaping Test
We are in the midst of an automotive electronics explosion. The combined move towards electric vehicles and autonomous driving is resulting in a rapid increase in both the number and complexity of electronic components integrated within a car. This rapid change is creating challenges for both device suppliers and integrators as they scramble to understand and define critical quality and reliability requirements and implementation solutions driven largely by the ISO 26262 standard. The Mentor Tessent product family offers a comprehensive set of semiconductor test solutions to address these evolving functional safety requirements. The Tessent solutions cover all parts of the chip (both digital and analog) and provide solutions for addressing both power-on as well as runtime test needs.
Calibre Parasitic Extraction: Complete Solutions for Automotive, IOT, and High Performance
The common theme in parasitic extraction is all designers require high accuracy, excellent Turn-Around Time (TAT), and usable/simulatable results. However, the details that define those essential elements of accuracy, performance, and simulation will vary greatly when you consider the needs of MEMs vs. Memory vs. Mobile applications. Additionally, process challenges such as FinFET, Multi-Patterning, and Multi-Corner impose additional concerns for the circuit designer. With Calibre xRC, xACT ,and xACT 3D, designers have a succinct set of options to select the right method for the parasitic extraction requirements. Calibre has field solver and rule-based techniques that are foundry qualified from 180nm to 7nm and can be used on large digital designs to small, single device analog cells. Calibre can provide atto-farad level accuracy in conjunction with robust resistance and inductance networks. Come to this session to see how Calibre xRC/xACT can be leveraged to give you a unique solution for your next design.
TECHNICAL SESSIONS IN BOOTH 1622
Demonstrating Functional Safety Compliance in Automotive IC Design
Functional Safety compliance has taken center stage in the automotive industry with rigorous, semiconductor-level processes and failure targets embodied on the ISO26262 standard. Certifying such compliance to the relevant ASIL tier, particularly in the face of growing design complexity and closer assessment scrutiny, calls for new paradigms and thinking. Traditionally, practitioners were able to rely on legacy architectures and use-models combined with targeted verification for selected logic units using customer-specific methodologies. For the highest safety levels, logic or component replication offered a way out. The enhanced scrutiny for level 3+ autonomous driving made possible by new IC architectures makes the former approach unattractive while the economics of the hardware costs make replication unviable. From a standards perspective, the preference for Fault simulation is made clear but safety engineers face a few obstacles to widespread adoption of Fault sims as the de-facto methodology. In this presentation, we will review some of the hurdles holding the industry back from conducting exhaustive fault campaigns and some innovative approaches to solving them. Also included is a review of acceleration strategies and best practices to enable them.
Veloce Brings Unique Solutions to the Automotive Market
Major trends such as ADAS/Autonomous driving, Connectivity and Advanced security are on the verge of revolutionizing the way automobiles are used. These trends bring significant implications for the design and verification of increasingly complex electronic systems. Join us for this session as we explore how the Veloce Emulation platform is positioned to deliver optimal verification solutions for the automotive market.
Using HLS to Accelerate Computer Vision for Autonomous Drive
The algorithms to teach a computer to see, understand and make decisions for ADAS and Autonomous Drive systems require a significant amount of parallel compute performance executing at the lowest possible power. This session will introduce of why HLS (High-level Synthesis) is such a good fit for computer vision and deep learning and how it can be used adapt rapidly changing algorithms and/or trained neural networks to low-power, high performance custom hardware accelerators.
