{"id":61,"date":"2020-07-06T15:02:42","date_gmt":"2020-07-06T19:02:42","guid":{"rendered":"https:\/\/blogs.mentor.com\/training\/?p=61"},"modified":"2026-03-27T08:20:49","modified_gmt":"2026-03-27T12:20:49","slug":"upcoming-functional-verification-webinar-july-14","status":"publish","type":"post","link":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/2020\/07\/06\/upcoming-functional-verification-webinar-july-14\/","title":{"rendered":"Upcoming Functional Verification Webinar (July 14)"},"content":{"rendered":"<p><strong>Get Your Bits Together: SystemVerilog Structures and Packages<\/strong><\/p>\n<p>Chris Spear, Principal Instructor will present a detailed description of structures and packages in the SystemVerilog language. You can model your hardware registers down to the bit level, or build complex data types that contain a mix of different elements such as 4-state logic, 2-state integers, real numbers, and enumerated types. In addition, you will be shown how you can combine related definitions for data types, parameters, classes, and more into a package that is easily shared and reused. We will also be discussing problems and best practices with packages. For more details, please see <a href=\"https:\/\/www.mentor.com\/products\/fv\/events\/get-your-bits-together--systemverilog-structures-and-packages\" target=\"_blank\" rel=\"noopener\">here<\/a>.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Get Your Bits Together: SystemVerilog Structures and Packages Chris Spear, Principal Instructor will present a detailed description of structures and&#8230;<\/p>\n","protected":false},"author":71643,"featured_media":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[311,313,315],"industry":[],"product":[],"coauthors":[],"class_list":["post-61","post","type-post","status-publish","format-standard","hentry","category-news","tag-systemverilog","tag-verification","tag-webinar"],"_links":{"self":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/61","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/users\/71643"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/comments?post=61"}],"version-history":[{"count":1,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/61\/revisions"}],"predecessor-version":[{"id":1424,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/posts\/61\/revisions\/1424"}],"wp:attachment":[{"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/media?parent=61"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/categories?post=61"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/tags?post=61"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/industry?post=61"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/product?post=61"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.sw.siemens.com\/xcelerator-academy\/wp-json\/wp\/v2\/coauthors?post=61"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}